MC9S12XET256MAL Freescale Semiconductor, MC9S12XET256MAL Datasheet - Page 468

• Manufacturer Part Number: MC9S12XET256MAL
• Description: MCU 16BIT 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 16KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• On-chip Adc: 16-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
START_XGATE
DUMMY_ISR
XGATE_DATA_FLASH
XGATE_DATA_SCI
XGATE_DATA_IDX
XGATE_DATA_MSG
XGATE_CODE_FLASH
XGATE_CODE_DONE
XGATE_CODE_FLASH_END
XGATE_DUMMY_ISR_XG
10.9.3
To simplify the implementation of a program stack the XGATE can be configured to set RISC core register
R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be defined:
One for threads of priority level 7 to 4 (refer to
468
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Stack Support
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
CPX
BLS
;###########################################
;#
;###########################################
MOVW #XGMCTL_ENABLE, XGMCTL
BRA
;###########################################
;#
;###########################################
RTI
CPU
;###########################################
;#
;###########################################
ALIGN 1
EQU
EQU
DW
EQU
DB
EQU
FCC
DB
;###########################################
;#
;###########################################
ALIGN 1
LDW
LDB
LDB
STB
LDB
STB
CMPL R4,#$0D
BEQ
RTS
LDL
STB
LDL
STB
RTS
EQU
MC9S12XE-Family Reference Manual , Rev. 1.23
#XGATE_CODE_FLASH_END
COPY_XGATE_CODE_LOOP
*
XGATE
*
*-XGATE_DATA_FLASH
SCI_REGS
*-XGATE_DATA_FLASH
XGATE_DATA_MSG
*-XGATE_DATA_FLASH
"Hello World!
$0D
R2,(R1,#XGATE_DATA_SCI)
R3,(R1,#XGATE_DATA_IDX)
R4,(R1,R3+)
R3,(R1,#XGATE_DATA_IDX)
R0,(R2,#(SCISR1-SCI_REGS))
R4,(R2,#(SCIDRL-SCI_REGS))
XGATE_CODE_DONE
R4,#$00
R4,(R2,#(SCICR2-SCI_REGS))
R3,#XGATE_DATA_MSG;reset R3
R3,(R1,#XGATE_DATA_IDX)
(XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
DUMMY INTERRUPT SERVICE ROUTINE
START XGATE
XGATE CODE
XGATE DATA
Section 10.3.1.5, “XGATE Initial Stack Pointer for
;enable XGATE
;pointer to SCI register space
;string pointer
;ASCII string
;CR
;SCI -> R2
;msg -> R3
;curr. char -> R4
;R3 -> idx
;initiate SCI transmit
;initiate SCI transmit
;disable SCI interrupts
#
#
#
#
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