MC68908GZ8CFAE Freescale Semiconductor, MC68908GZ8CFAE Datasheet - Page 172

• Manufacturer Part Number: MC68908GZ8CFAE
• Description: IC MCU 8K FLASH 8MHZ CAN 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: ESCI, SPI, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 48LQFP
• Family Name: HC08
• Maximum Speed: 8 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
ILAD — Illegal Address Reset Bit
MODRST — Monitor Mode Entry Module Reset Bit
LVI — Low-Voltage Inhibit Reset Bit
14.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
14.3.1 Effects
An interrupt:
172
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1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR since any reset
1 = Last reset caused by forced monitor mode entry.
0 = POR or read of SRSR since any reset
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR since any reset
Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
Loads the program counter with a user-defined vector address
STACKING
1. High byte of index register is not stacked.
ORDER
5
4
3
2
1
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Figure 14-3. Interrupt Stacking Order
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
INDEX REGISTER (LOW BYTE)
CONDITION CODE REGISTER
ACCUMULATOR
•
•
•
•
•
•
(1)
$00FF DEFAULT ADDRESS ON RESET
1
2
3
4
5
UNSTACKING
ORDER
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