MC68908GZ8CFAE Freescale Semiconductor, MC68908GZ8CFAE Datasheet - Page 269
![IC MCU 8K FLASH 8MHZ CAN 48-LQFP](/photos/12/37/123730/mc68908gz8cfae_sml.jpg)
MC68908GZ8CFAE
Manufacturer Part Number
MC68908GZ8CFAE
Description
IC MCU 8K FLASH 8MHZ CAN 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
ESCI, SPI, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
48LQFP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC68908GZ8CFAE
Manufacturer:
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Part Number:
MC68908GZ8CFAE
Manufacturer:
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TOVx — Toggle On Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
Freescale Semiconductor
When channel x is an output compare channel, this read/write bit controls the behavior of the channel x
output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As
after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
MSxB:MSxA ELSxB:ELSxA
X0
X1
00
00
00
01
01
01
1X
1X
1X
Before enabling a TIM channel register for input capture operation, make
sure that the PTD/TCHx pin is stable for at least two bus clocks.
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX
TCHx
OVERFLOW
00
00
01
10
11
01
10
11
01
10
11
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Table 19-3. Mode, Edge, and Level Selection
COMPARE
PERIOD
OUTPUT
Figure 19-12. CHxMAX Latency
OVERFLOW
Output compare
Buffered output
or buffered
compare
or PWM
capture
Output
preset
Mode
PWM
Figure 19-12
Input
COMPARE
OUTPUT
NOTE
NOTE
OVERFLOW
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
shows, the CHxMAX bit takes effect in the cycle
COMPARE
OUTPUT
OVERFLOW
Configuration
COMPARE
OUTPUT
OVERFLOW
I/O Registers
269
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