MC68908GZ8CFAE Freescale Semiconductor, MC68908GZ8CFAE Datasheet - Page 187
![IC MCU 8K FLASH 8MHZ CAN 48-LQFP](/photos/12/37/123730/mc68908gz8cfae_sml.jpg)
MC68908GZ8CFAE
Manufacturer Part Number
MC68908GZ8CFAE
Description
IC MCU 8K FLASH 8MHZ CAN 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
ESCI, SPI, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
48LQFP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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15.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control
register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control
register 3 (SCC3) is the ninth bit (bit 8).
15.4.2.2 Character Transmission
During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
To initiate an ESCI transmission:
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit (LSB) position of
the transmit shift register. A logic 1 stop bit goes into the most significant bit (MSB) position.
The ESCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the ESCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition,
logic 1. If at any time software clears the ENSCI bit in ESCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
15.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break
character. For TXINV = 0 (output not inverted), a transmitted break character contains all logic 0s and has
no start, stop, or parity bit. Break character length depends on the M bit in SCC1 and the LINR bits in
SCBR. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit
shift register. After software clears the SBK bit, the shift register finishes transmitting the last break
character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character
guarantees the recognition of the start bit of the next character.
When LINR is cleared in SCBR, the ESCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be, resulting in a total of 10 or 11
consecutive logic 0 data bits. When LINR is set in SCBR, the ESCI recognizes a break character when a
start bit is followed by 9 or 10 logic 0 data bits and a logic 0 where the stop bit should be, resulting in a
total of 11 or 12 consecutive logic 0 data bits.
Freescale Semiconductor
1. Enable the ESCI by writing a logic 1 to the enable ESCI bit (ENSCI) in ESCI control register 1
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in ESCI control register
3. Clear the ESCI transmitter empty bit (SCTE) by first reading ESCI status register 1 (SCS1) and
4. Repeat step 3 for each subsequent transmission.
(SCC1).
2 (SCC2).
then writing to the SCDR. For 9-bit data, also write the T8 bit in SCC3.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Functional Description
187
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