MC68908GZ8CFAE Freescale Semiconductor, MC68908GZ8CFAE Datasheet - Page 217
![IC MCU 8K FLASH 8MHZ CAN 48-LQFP](/photos/12/37/123730/mc68908gz8cfae_sml.jpg)
MC68908GZ8CFAE
Manufacturer Part Number
MC68908GZ8CFAE
Description
IC MCU 8K FLASH 8MHZ CAN 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
ESCI, SPI, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
48LQFP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
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MC68908GZ8CFAE
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Quantity:
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Part Number:
MC68908GZ8CFAE
Manufacturer:
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16.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset continues to be asserted for an additional 32 cycles at which point
the reset vector will be fetched. See
illegal opcode, COP timeout, LVI, or POR. See
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
16.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
Freescale Semiconductor
•
•
•
•
•
•
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in
CGMXCLK
RST
IAB
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Figure 16-6. Sources of Internal Reset
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
Figure 16-5. Internal Reset Timing
RST PULLED LOW BY MCU
Figure
32 CYCLES
MODRST
COPRST
16-5. An internal reset can be caused by an illegal address,
POR
LVI
Figure
NOTE
16-6.
32 CYCLES
INTERNAL RESET
Figure
VECTOR HIGH
Reset and System Initialization
16-5.
217
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