MC9S08GB60ACFUE Freescale Semiconductor, MC9S08GB60ACFUE Datasheet
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MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A Data Sheet HCS08 Microcontrollers MC9S08GB60A Rev. 2 07/2008 freescale.com ...
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MC9S08GB60A Data Sheet Covers: MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A MC9S08GB60A Rev. 2 07/2008 ...
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... This product incorporates SuperFlash Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005-2008. All rights reserved. 6 Description of Changes Initial public release. Added a footnote to RTI of Table 3.2; Added RTI description to Section 3.5.6; ...
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... Chapter 14 Analog-to-Digital Converter (S08ATDV3 223 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Appendix A Electrical Characteristics 261 Appendix B EB652: Migrating from the GB60 Series to the GB60A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Appendix C Ordering Information and Mechanical Drawings . . . . . . . . . . 287 Freescale Semiconductor List of Chapters Title MC9S08GB60A Data Sheet, Rev. 2 Page 3 ...
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... Stop2 Mode ......................................................................................................................37 3.6.3 Stop3 Mode ......................................................................................................................38 3.6.4 Active BDM Enabled in Stop Mode ................................................................................38 3.6.5 LVD Enabled in Stop Mode .............................................................................................39 3.6.6 On-Chip Peripheral Modules in Stop Modes ...................................................................39 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation MC9S08GB60A Data Sheet, Rev. 2 ...
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... LVD Interrupt Operation .................................................................................................71 5.6.4 Low-Voltage Warning (LVW) .........................................................................................71 5.7 Real-Time Interrupt (RTI) ...............................................................................................................71 5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................72 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................73 8 Title Chapter 4 Memory Chapter 5 MC9S08GB60A Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... Introduction ...................................................................................................................................105 7.1.1 Features ..........................................................................................................................106 7.1.2 Modes of Operation .......................................................................................................107 7.2 Oscillator Pins ...............................................................................................................................107 7.2.1 EXTAL— External Reference Clock / Oscillator Input ................................................107 7.2.2 XTAL— Oscillator Output ............................................................................................107 Freescale Semiconductor Title Chapter 6 Parallel Input/Output Chapter 7 MC9S08GB60A Data Sheet, Rev. 2 Page 9 ...
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... Features ..........................................................................................................................129 8.2 Programmer’s Model and CPU Registers .....................................................................................130 8.2.1 Accumulator (A) ............................................................................................................130 8.2.2 Index Register (H:X) .....................................................................................................130 8.2.3 Stack Pointer (SP) ..........................................................................................................131 8.2.4 Program Counter (PC) ...................................................................................................131 8.2.5 Condition Code Register (CCR) ....................................................................................131 10 Title Chapter 8 MC9S08GB60A Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... Features .........................................................................................................................................155 10.3 TPM Block Diagram .....................................................................................................................157 10.4 Pin Descriptions ............................................................................................................................158 10.4.1 External TPM Clock Sources ........................................................................................158 10.4.2 TPMxCHn — TPMx Channel n I/O Pins ......................................................................158 10.5 Functional Description ..................................................................................................................158 Freescale Semiconductor Title Chapter 9 Keyboard Interrupt (S08KBIV1) Chapter 10 Timer/PWM (S08TPMV1) MC9S08GB60A Data Sheet, Rev. 2 ...
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... Data Sampling Technique .............................................................................185 11.3.3.2 Receiver Wakeup Operation .........................................................................185 11.3.4 Interrupts and Status Flags .............................................................................................186 11.3.5 Additional SCI Functions ..............................................................................................187 11.3.5.1 8- and 9-Bit Data Modes ...............................................................................187 11.3.5.2 Stop Mode Operation ....................................................................................187 11.3.5.3 Loop Mode ....................................................................................................188 12 Title Chapter 11 MC9S08GB60A Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... SCL — Serial Clock Line ..............................................................................................208 13.2.2 SDA — Serial Data Line ...............................................................................................208 13.3 Register Definition ........................................................................................................................208 13.3.1 IIC Address Register (IIC1A) ........................................................................................209 13.3.2 IIC Frequency Divider Register (IIC1F) .......................................................................209 13.3.3 IIC Control Register (IIC1C) .........................................................................................212 Freescale Semiconductor Title Chapter 12 Chapter 13 MC9S08GB60A Data Sheet, Rev. 2 Page ...
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... ATD Registers and Control Bits ....................................................................................................233 14.6.1 ATD Control (ATDC) ....................................................................................................234 14.6.2 ATD Status and Control (ATD1SC) ..............................................................................236 14.6.3 ATD Result Data (ATD1RH, ATD1RL) ........................................................................237 14 Title Chapter REFH REFL ....................................................................... 227 , V DDAD SSAD ........................................................................... 227 MC9S08GB60A Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... Debug Status Register (DBGS) ....................................................................260 A.1 Introduction ...................................................................................................................................261 A.2 Absolute Maximum Ratings ..........................................................................................................261 A.3 Thermal Characteristics .................................................................................................................262 A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................263 A.5 DC Characteristics .........................................................................................................................263 Freescale Semiconductor Title Chapter 15 Development Support Appendix A Electrical Characteristics MC9S08GB60A Data Sheet, Rev. 2 ...
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... B.5 Internal Clock Generator: Low-Power Oscillator Maximum Frequency ......................................284 B.6 Internal Clock Generator: Loss-of-Clock Disable Option ............................................................284 B.7 System Device Identification Register ..........................................................................................285 Ordering Information and Mechanical Drawings C.1 Ordering Information ....................................................................................................................287 C.2 Mechanical Drawings ....................................................................................................................288 16 Title Appendix B Appendix C MC9S08GB60A Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... Optional computer operating properly (COP) reset — Low-voltage detection with reset or interrupt — Illegal opcode detection with reset — Illegal address detection with reset (some devices don’t have illegal addresses) Freescale Semiconductor Chapter 15, “Development MC9S08GB60A Data Sheet, Rev. 2 Support”) ...
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... MC9S08GBxxA • 48-pin quad flat package, no lead (QFN) — MC9S08GTxxA • 44-pin quad flat package (QFP) — MC9S08GTxxA • 42-pin skinny dual in-line package (SDIP) — MC9S08GTxxA 18 Table 1-1 for device specific information) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... MC9S08GT32A 32K 1 The 48-pin QFN package has one 3-channel and one 2-channel 16-bit TPM. 1.3 MCU Block Diagrams These block diagrams show the structure of the MC9S08GBxxA/GTxxA MCUs. Freescale Semiconductor RAM TPM 4K One 3-channel and one 5-channel, 16-bit timer 2K One 3-channel and one ...
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... PTC1/RxD2 SCL1 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 5 PTD4/TPM2CH1 PTD3/TPM2CH0 PTD2/TPM1CH2 3 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 SPSCK1 PTE5/SPSCK1 MOSI1 PTE4/MOSI1 MISO1 PTE3/MISO1 SS1 PTE2/SS1 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 8 PTF7–PTF0 4 PTG7–PTG4 PTG3 EXTAL PTG2/EXTAL XTAL PTG1/XTAL BKGD PTG0/BKGD/MS for complete details. Freescale Semiconductor ...
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... The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module Control bits inside the ICG determine which source is connected. Freescale Semiconductor Table 1-2. Block Versions Module Analog-to-Digital Converter (ATD) Internal Clock Generator (ICG) ...
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... Otherwise the fixed-frequency clock will be BUSCLK. • ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. 22 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev ...
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... PTC4 7 PTC5 8 PTC6 9 PTC7 10 PTF2 11 PTF3 12 PTF4 13 PTE0/TxD1 14 PTE1/RxD1 15 IRQ Figure 2-1. MC9S08GBxxA in 64-Pin LQFP Package MC9S08GB60A Data Sheet, Rev PTA2/KBI1P2 47 PTA1/KBI1P1 46 PTA0/KBI1P0 45 PTF7 44 PTF6 43 PTF5 42 V REFL 41 V REFH 40 PTB7/AD1P7 39 PTB6/AD1P6 38 PTB5/AD1P5 37 PTB4/AD1P4 PTB3/AD1P3 36 35 PTB2/AD1P2 34 PTB1/AD1P1 PTB0/AD1P0 Freescale Semiconductor ...
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... PTC0/TxD2 3 PTC1/RxD2 4 PTC2/SDA1 5 PTC3/SCL1 6 PTC4 7 PTC5 8 PTC6 PTC7 9 10 PTE0/TxD1 11 PTE1/RxD1 12 IRQ Figure 2-2. MC9S08GTxxA in 48-Pin QFN Package Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Chapter 2 Pins and Connections 36 PTA1/KBI1P1 35 PTA0/KBI1P0 34 V REFL 33 V REFH 32 PTB7/AD1P7 31 PTB6/AD1P6 30 PTB5/AD1P5 29 PTB4/AD1P4 28 PTB3/AD1P3 27 PTB2/AD1P2 ...
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... Chapter 2 Pins and Connections 1 RESET PTC0/TxD2 PTC1/RxD2 PTC2/SDA1 PTC3/SCL1 PTC4 PTC5 PTC6 PTE0/TxD1 PTE1/RxD1 11 IRQ Figure 2-3. MC9S08GTxxA in 44-Pin QFP Package MC9S08GB60A Data Sheet, Rev PTA1/KBI1P1 32 PTA0/KBI1P0 31 V REFL 30 V REFH 29 PTB7/AD1P7 28 PTB6/AD1P6 27 PTB5/AD1P5 26 PTB4/AD1P4 PTB3/AD1P3 25 24 PTB2/AD1P2 23 PTB1/AD1P1 Freescale Semiconductor ...
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... Figure 2-4. . MC9S08GTxxA in 42-Pin SDIP Package 2.3 Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08GBxxA application systems. MC9S08GTxxA connections will be similar except for the number of I/O pins available. A more detailed discussion of system connections follows. Freescale Semiconductor V 1 DDAD V 2 SSAD ...
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... PTB3/AD1P3 PORT B PTB4/AD1P4 PTB5/AD1P5 I/O AND PTB6/AD1P6 PTB7/AD1P7 PERIPHERAL INTERFACE TO PTC0/TxD2 PTC1/RxD2 APPLICATION PTC2/SDA1 SYSTEM PTC3/SCL1 PORT C PTC4 PTC5 PTC6 PTC7 PTD0/TPM1CH0 PTD1/TPM1CH1 PTD2/TPM1CH2 PTD3/TPM2CH0 PORT D PTD4/TPM2CH1 PTD5/TPM2CH2 PTD6/TPM2CH3 PTD7/TPM2CH4 PTE0/TxD1 PTE1/RxD1 PTE2/SS1 PTE3/MISO1 PORT E PTE4/MOSI1 PTE5/SPSCK1 PTE6 PTE7 Freescale Semiconductor ...
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... RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background Freescale Semiconductor Chapter 7, “Internal Clock Generator (when used) and R S MC9S08GB60A Data Sheet, Rev ...
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... To prevent extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float released, and sampled again approximately 38 Self_reset NOTE MC9S08GB60A Data Sheet, Rev. 2 Figure 2-4 for Freescale Semiconductor ...
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... Similarly, when IRQ is configured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. Freescale Semiconductor 2-1. Table 2-1. Pin Sharing References Chapter 2, “ ...
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... When pin is configured for SCI function, pin is configured for partial output drive. SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC Not available on 42-pin package SWC SWC Not available on 42-pin package MC9S08GB60A Data Sheet, Rev. 2 Comments pins — IRQ should Freescale Semiconductor SS1 ...
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... I/O N PTG7 I SWC is software controlled slew rate, the register is associated with the respective port. 2 SWC is software controlled pullup resistor, the register is associated with the respective port. Freescale Semiconductor Table 2-2. Signal Properties (continued) Output 2 Pull-Up 1 Slew SWC SWC Not available on 42-pin package ...
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... Chapter 2 Pins and Connections 34 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint Freescale Semiconductor MC9S08GB60A Data Sheet, Rev ...
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... The active background mode is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time. When the MC9S08GBxxA/GTxxA is shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the flash memory is initially programmed ...
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... When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator low-power standby state the ATD. Upon entry Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...
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... When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. 38 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, Freescale Semiconductor Chapter 15, “Development Support,” section of this data sheet. If ENBDM ...
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... SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from stop and must be reinitialized. 40 Section 3.6.3, “Stop3 Mode,” for specific information on MC9S08GB60A Data Sheet, Rev. 2 Section 3.6.1, “Stop1 . No conversion Freescale Semiconductor ...
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... If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Chapter 3 Modes of Operation 41 ...
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... Chapter 3 Modes of Operation 42 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Nonvolatile registers (0xFFB0 through 0xFFBF) DIRECT PAGE REGISTERS 4096 BYTES FLASH 1920 BYTES HIGH PAGE REGISTERS FLASH 59348 BYTES MC9S08GB60A/MC9S08GT60A Figure 4-1. MC9S08GBxxA/GTxxA Memory Map Freescale Semiconductor 0x0000 DIRECT PAGE REGISTERS 0x007F 0x0080 RAM 0x107F 0x1080 0x17FF 0x1800 HIGH PAGE REGISTERS ...
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... Low Voltage Detect IRQ SWI Reset MC9S08GB60A Data Sheet, Rev. 2 Chapter 5, “Resets, Vector Name Vrti Viic1 Vatd1 Vkeyboard1 Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi1 Vtpm2ovf Vtpm2ch4 Vtpm2ch3 Vtpm2ch2 Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vswi Vreset Freescale Semiconductor ...
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... Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode which only and Table 4-4 the whole address in column one is shown in bold ...
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... KBIPE0 SBR11 SBR10 SBR9 SBR3 SBR2 SBR1 WAKE ILT RWU ORIE NEIE FEIE SBR11 SBR10 SBR9 SBR3 SBR2 SBR1 WAKE ILT RWU ORIE NEIE FEIE Freescale Semiconductor Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 ...
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... PTGPE PTGPE7 0x0046 PTGSE PTGSE7 0x0047 PTGDD PTGDD7 0x0048 ICGC1 HGO 0x0049 ICGC2 LOLRE 0x004A ICGS1 0x004B ICGS2 0 0x004C ICGFLTU 0 0x004D ICGFLTL 0x004E ICGTRM 0x004F Reserved 0 Freescale Semiconductor SPE SPTIE MSTR 0 0 MODFEN SPPR2 SPPR1 SPPR0 0 SPTEF MODF TOIE CPWMS ...
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... ELS3B ELS3A ELS4B ELS4A — — — — — — Freescale Semiconductor Bit 0 Bit 0 Bit 0 — — RXAK — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — ...
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... NVPROT and NVOPT in the nonvolatile register area of the flash memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Freescale Semiconductor 4-3, are accessed much less often than other I/O and control registers Table 4-3. High-Page Register Summary ...
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... FPS1 — — — FNORED 0 0 ;point one past RAM ;SP<-(H:X-1) MC9S08GB60A Data Sheet, Rev — — — — — — FPS0 0 0 — — — SEC01 Section 4.5, “Security” for a detailed Freescale Semiconductor Bit 0 — — 0 — SEC00 ...
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... For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 4.4.1 Features Features of the flash memory include: • ...
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... The command sequence must be completed by clearing FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any flash commands. This must be done only once following a reset. 52 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst Freescale Semiconductor START 0 ...
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... Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. (2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure 4-3. Flash Burst Program Flowchart MC9S08GB60A Data Sheet, Rev. 2 Only required once after reset. ERROR EXIT Freescale Semiconductor ...
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... One use for block protection is to block protect an area of flash memory for a bootloader program. This bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. Freescale Semiconductor NVPROT)”). MC9S08GB60A Data Sheet, Rev. 2 Chapter 4 Memory ...
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... Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a flash program or erase command. 56 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. Freescale Semiconductor Table 4-3 MC9S08GB60A Data Sheet, Rev. 2 ...
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... MC9S08GB60A Data Sheet, Rev DIV2 DIV1 DIV0 0 0 Eqn. 4-1 Eqn. 4-2 (5 μs Min, 6.7 μs Max) 5.2 μs 5 μs 5 μs 5 μs 5 μs 5 μs 5 μs 6.7 μs Freescale Semiconductor 0 0 ...
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... For more detailed information about security, refer to Section 4.5, “Security.” 00 Secure 01 Secure 10 Unsecured 11 Secure SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of flash. Freescale Semiconductor Figure 4-5. Flash Options Register (FOPT) Table 4-8 ...
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... Entire flash memory is block protected (no program or erase allowed). 1 Any flash location, not otherwise block protected or secured, may be erased or programmed KEYACC Table 4-9. FCNFG Field Descriptions Description Section 4. FPS2 FPS1 FPS0 (1) (1) (1) Table 4-10. FPROT Field Descriptions Description MC9S08GB60A Data Sheet, Rev “Security.” Freescale Semiconductor ...
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... No redirection if FPOPEN = 0, or FNORED = 1. 2 Reset vector is not redirected. 3 32K and 60K devices only. 4 60K devices only. Freescale Semiconductor Description Table 4-11). Protected flash locations cannot be erased or Table 4-11. High Address Protected Block Protected Block Size 0xFE00–0xFFFF 512 bytes 0xFC00– ...
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... After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the flash array is completely erased (all 0xFF FPVIOL FACCERR Figure 4-8. Flash Status Register (FSTAT) Table 4-12. FSTAT Field Descriptions Description MC9S08GB60A Data Sheet, Rev FBLANK Section 4.4.5, “Access Errors.” FACCERR Freescale Semiconductor ...
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... Mass erase (all flash) All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. Freescale Semiconductor Execution” for a detailed discussion of flash programming 5 ...
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... Chapter 4 Memory 64 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
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... SP is forced to 0x00FF at reset. The MC9S08GBxxA/GTxxA has seven sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) • Computer operating properly (COP) timer Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Table 5-1) 65 ...
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... If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond until and unless the local interrupt enable is set enable the interrupt. The I bit 66 selected. The reset pin is driven low for 34 Self_reset Section 5.8.4, “System Options Register MC9S08GB60A Data Sheet, Rev. 2 (SOPT)” for Freescale Semiconductor ...
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... SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE MC9S08GB60A Data Sheet, Rev ...
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... INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW ² ² TOWARD HIGHER ADDRESSES ² * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame NOTE MC9S08GB60A Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT – 0 All DD Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction, stack the PCL, PCH and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration MC9S08GB60A Data Sheet, Rev. 2 ...
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... TPM2 channel 1 CH0IE TPM2 channel 0 TOIE TPM1 overflow CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 LOLRE/LOCRE ICG LVDIE Low-voltage detect IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect — External pin — Illegal opcode Freescale Semiconductor ...
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... RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used. When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration level. Both the POR bit and the LVD bit in SRS are set ...
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... Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” 72 Chapter 4, “Memory” of this data sheet for the absolute MC9S08GB60A Data Sheet, Rev. 2 (SRTISC),” for detailed Freescale Semiconductor ...
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... The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...
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... Reset caused by an illegal opcode COP ILOP Writing any value to SIMRS address clears COP watchdog timer (1) (1) Note Note Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Field Descriptions Description MC9S08GB60A Data Sheet, Rev ICG LVD (1) 0 Note 0 Freescale Semiconductor ...
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... Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an BDFR external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description 5 ...
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... BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This pin always defaults to BKGD/MS function after any reset. 0 BKGD pin disabled. 1 BKGD pin enabled STOPE Table 5-5. SOPT Field Descriptions Description 13 cycles of BUSCLK). 18 cycles of BUSCLK). MC9S08GB60A Data Sheet, Rev BKGDPE Freescale Semiconductor ...
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... Figure 5-7. System Device Identification Register Low (SDIDL) Field 3:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08GBxxA/GTxxA is hard coded to the value 0x002. See also ID bits in Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration REV1 ...
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... Characteristics,” for the tolerance on these values. MC9S08GB60A Data Sheet, Rev RTIS2 RTIS RTIS External Clock Source Period = t ext Disable periodic wakeup timer t x 256 ext t x 1024 2048 4096 8192 ext t x 16384 ext t x 32768 ex Table A-9 for details. Freescale Semiconductor ...
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... Low-voltage detect enabled during stop mode. 2 Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration LVDIE ...
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... U = Unaffected by reset transitions below the trip point or after reset and V Supply Table 5-11. SPMSC2 Field Descriptions Description = V ). LVD LVDL = V ). LVD LVDH = V ). LVW LVWL = V ). LVW LVWH MC9S08GB60A Data Sheet, Rev PPDF PDC PPDACK already below V Supply ). LVD LVW Freescale Semiconductor 0 PPDC LVW ). ...
Page 81
... Freescale Semiconductor Connections,” for more information about the logic and NOTE MC9S08GB60A Data Sheet, Rev. 2 ...
Page 82
... SDA1 PTC2/SDA1 SCL1 PTC1/RxD2 SCL1 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 5 PTD4/TPM2CH1 PTD3/TPM2CH0 PTD2/TPM1CH2 3 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 SPSCK1 PTE5/SPSCK1 MOSI1 PTE4/MOSI1 MISO1 PTE3/MISO1 SS1 PTE2/SS1 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 8 PTF7–PTF0 4 PTG7–PTG4 PTG3 EXTAL PTG2/EXTAL XTAL PTG1/XTAL BKGD PTG0/BKGD/MS Freescale Semiconductor ...
Page 83
... KBI inputs will be forced to act as inputs. Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction (PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to I/O Controls,” for more information about general-purpose I/O control. Freescale Semiconductor PTA6/ ...
Page 84
... Chapter 13, “Inter-Integrated Circuit MC9S08GB60A Data Sheet, Rev. 2 Chapter 9, “Keyboard Interrupt 2 1 Bit 0 PTB2/ PTB1/ PTB0/ AD1P2 AD1P1 AD1P0 Section 6.4, “Parallel for more information 2 1 Bit 0 PTC2/ PTC1/ PTC0/ SDA1 RxD2 TxD2 Section 6.4, “Parallel (S08SCIV1),” (S08IICV1),” Freescale Semiconductor for ...
Page 85
... When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5 serves as the SPI clock pin (SPSCK1). Refer to more information about using PTE5–PTE2 as SPI pins. Freescale Semiconductor ...
Page 86
... Configuration”, and Chapter 15, “Development (S08IICV1)” for more information about using these pins as MC9S08GB60A Data Sheet, Rev Bit 0 PTF2 PTF1 PTF0 Section 6.4, “Parallel 2 1 Bit 0 PTG2/ PTG1/ PTG0/ EXTAL XTAL BKGD/MS Section 6.4, “Parallel Operation”, Support” for Freescale Semiconductor ...
Page 87
... Not all peripheral modules’ outputs have slew rate control; refer to Chapter 2, “Pins and rate control. Freescale Semiconductor Connections” for more information about which pins have slew MC9S08GB60A Data Sheet, Rev. 2 Chapter 6 Parallel Input/Output ...
Page 88
... If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of PTAD will return the logic value of the corresponding pin, provided PTADD MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 89
... When any of bits 7 through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor PTAD5 ...
Page 90
... Output driver enabled for port A bit n and PTAD reads return the contents of PTADn PTASE5 PTASE4 PTASE3 Table 6-3. PTASE Field Descriptions Description PTADD5 PTADD4 PTADD3 Table 6-4. PTADD Field Descriptions Description MC9S08GB60A Data Sheet, Rev PTASE2 PTASE1 PTASE0 PTADD2 PTADD1 PTADD0 Freescale Semiconductor ...
Page 91
... Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether PTBPE[7:0] internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor PTBD5 PTBD4 ...
Page 92
... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBSE5 PTBSE4 PTBSE3 Table 6-7. PTBSE Field Descriptions Description PTBDD5 PTBDD4 PTBDD3 Table 6-8. PTBDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev PTBSE2 PTBSE1 PTBSE0 PTBDD2 PTBDD1 PTBDD0 Freescale Semiconductor ...
Page 93
... Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor ...
Page 94
... PTCPE4 PTCPE3 Table 6-10. PTCPE Field Descriptions Description PTCSE5 PTCSE4 PTCSE3 Table 6-11. PTCSE Field Descriptions Description PTCDD5 PTCDD4 PTCDD3 Table 6-12. PTCDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 95
... Pullup Enable for Port D Bits — For port D pins that are inputs, these read/write control bits determine whether PTDPE[7:0] internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor PTDD5 PTDD4 ...
Page 96
... Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn PTDSE5 PTDSE4 PTDSE3 Table 6-15. PTDSE Field Descriptions Description PTDDD5 PTDDD4 PTDDD3 Table 6-16. PTDDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev PTDSE2 PTDSE1 PTDSE0 PTDDD2 PTDDD1 PTDDD0 Freescale Semiconductor ...
Page 97
... Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor ...
Page 98
... PTEPE4 PTEPE3 Table 6-18. PTEPE Field Descriptions Description PTESE5 PTESE4 PTESE3 Table 6-19. PTESE Field Descriptions Description PTEDD5 PTEDD4 PTEDD3 Table 6-20. PTEDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev PTEPE2 PTEPE1 PTEPE0 PTESE2 PTESE1 PTESE0 PTEDD2 PTEDD1 PTEDD0 Freescale Semiconductor ...
Page 99
... Pullup Enable for Port F Bits — For port F pins that are inputs, these read/write control bits determine whether PTFPE[7:0] internal pullup devices are enabled. For port F pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor 5 4 PTFD5 PTFD4 PTFD3 ...
Page 100
... Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0. 100 PTFSE5 PTFSE4 PTFSE3 Table 6-23. PTFSE Field Descriptions Description PTFDD5 PTFDD4 PTFDD3 Table 6-24. PTFDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev PTFSE2 PTFSE1 PTFSE0 PTFDD2 PTFDD1 PTFDD0 Freescale Semiconductor ...
Page 101
... Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether PTGPE[7:0] internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor 5 4 PTGD5 PTGD4 PTGD3 ...
Page 102
... Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. 102 PTGSE5 PTGSE4 PTGSE3 Table 6-27. PTGSE Field Descriptions Description PTGDD5 PTGDD4 PTGDD3 Table 6-28. PTGDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev PTGSE2 PTGSE1 PTGSE0 PTGDD2 PTGDD1 PTGDD0 Freescale Semiconductor ...
Page 103
... CPU * ICGLCLK is the alternate BDC clock source for the MC9S08GBxxA/GTxxA. Figure 7-1. System Clock Distribution Diagram Freescale Semiconductor recommends that flash location $FFBE be reserved to store a nonvolatile version of ICGTRM. This will allow debugger and programmer vendors to perform a manual trim operation and store the resultant ICGTRM value for users to access at a later time. ...
Page 104
... SDA1 PTC2/SDA1 SCL1 PTC1/RxD2 SCL1 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 5 PTD4/TPM2CH1 PTD3/TPM2CH0 PTD2/TPM1CH2 3 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 SPSCK1 PTE5/SPSCK1 MOSI1 PTE4/MOSI1 MISO1 PTE3/MISO1 SS1 PTE2/SS1 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 8 PTF7–PTF0 4 PTG7–PTG4 PTG3 EXTAL PTG2/EXTAL XTAL PTG1/XTAL BKGD PTG0/BKGD/MS Freescale Semiconductor ...
Page 105
... Status bits provide information when the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. Freescale Semiconductor ICG SELECT ...
Page 106
... Separate self-clocked source for real-time interrupt • Trimmable internal clock source supports SCI communications without additional external components • Automatic FLL engagement after lock is acquired • Selectable low-power/high-gain oscillator modes 106 Section 7.4, “Initialization/Application MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 107
... If upon the first write to ICGC1, either FEE mode or FBE mode is selected, this pin functions as the output of the oscillator circuit. If upon the first write to ICGC1, either FEI mode or SCM mode is selected, this Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Internal Clock Generator (S08ICGV2) ...
Page 108
... Recommended component values are listed in Figure 7-5. External Frequency Reference Connection 108 ICG EXTAL V SS CLOCK INPUT Figure 7-4. External Clock Connections Appendix A, “Electrical ICG EXTAL CRYSTAL OR RESONATOR MC9S08GB60A Data Sheet, Rev. 2 Figure 7-4. XTAL NOT CONNECTED Characteristics.” XTAL R S Freescale Semiconductor ...
Page 109
... Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state temporarily until the DCO is stable (DCOS = 1). • CLKS bits are written from X1 to 00. • CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1). Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Internal Clock Generator (S08ICGV2) 109 ...
Page 110
... OSCILLATOR FILTER FLL ANALOG CLKST PULSE COUNTER RESET AND INTERRUPT CONTROL LOCD LOCS ERCS ICGIF LOLRE LOCRE MC9S08GB60A Data Sheet, Rev. 2 which is nominally 8 MHz. If this RFD REDUCED ICGOUT FREQUENCY DIVIDER (R) ICGDCLK 1x 2x FREQUENCY- LOCKED LOOP (FLL) ICG2DCLK IRQ RESET Freescale Semiconductor ...
Page 111
... CLKS = 11 and ERCS and DCOS are both high. • The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11. Freescale Semiconductor or less than the minimum n unlock (max) and greater than nlock (min) for a given number of samples, as MC9S08GB60A Data Sheet, Rev. 2 ...
Page 112
... As soon as the FLL has locked, Δn (min) and n lock lock (max) to remain locked. If Δn goes outside this range unlock MC9S08GB60A Data Sheet, Rev less than lock / (2×R). This ICGDCLK (max) and greater lock /R. In FLL engaged external ICGDCLK Freescale Semiconductor ...
Page 113
... If ENABLE is high (waiting for external crystal start-up after exiting stop). 2 DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode. Freescale Semiconductor and f , respectively, the LOCS status bit will be set to indicate the error. LOD ...
Page 114
... FBE to SCM ICGDCLK/R — ICGDCLK/R — DCOS = 0 or ICGDCLK/R — ICGDCLK/R DCOS = 1 ICGDCLK/R — ERCS = 1 — ERCS = 1 and 3 DCOS = 1 ERCS = 1 and (2) DCOS = 1 Freescale Semiconductor Reason CLKS1 = CLKST — ERCS = 0 — DCOS = 0 ERCS = 0 ERCS = 0 — ERCS = 0 — LOCS = 1 & ERCS = 1 — — ...
Page 115
... ICG. For some applications, the serial communication link may dictate the accuracy of the clock reference. For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. Freescale Semiconductor Table Table 7-5). ...
Page 116
... IRG Range = ext Range = does not exceed f ICGOUT MC9S08GB60A Data Sheet, Rev. 2 Clock Reference Source = External < 20 MHz Bus range <= 8 MHz when crystal or resonator is P Note Typical f ICGOUT NA 8 MHz out of reset NA 64 Typical f = 243 kHz IRG ICGDCLKmax. Freescale Semiconductor = ...
Page 117
... Register Bit 7 ICGC1 HGO RANGE ICGC2 LOLRE ICGS1 CLKST ICGS2 0 ICGFLTU 0 ICGFLTL ICGTRM = Unimplemented or Reserved Freescale Semiconductor Table 7-5. MFD and RFD Decode Table RFD 4 000 6 001 8 010 10 011 12 100 14 101 16 110 18 111 REFS ...
Page 118
... Oscillator using crystal or resonator is requested FLL engaged, external reference clock mode Oscillator disabled in stop modes Loss-of-clock detection enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08GB60A Data Sheet, Rev Bus = 32 kHz Freescale Semiconductor Eqn. 7-1 Eqn. 7-2 ...
Page 119
... REFS 1 Bits 4:3 CLKS 11 Bit 2 OSCSTEN 0 Bit 1 LOCD 0 Bit 0 0 Freescale Semiconductor QUICK RECOVERY FROM STOP RECOVERY FROM STOP3 OSCSTEN = 1 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR AND EXTERNAL CIRCUITRY ...
Page 120
... Figure 7-9. ICG Initialization and Stop Recovery for Example #2 120 Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock RECOVERY FROM STOP3 INITIALIZE ICG SERVICE INTERRUPT ICG1 = $7A ICG2 = $30 SOURCE (f CHECK NO LOCK = 1? FLL LOCK STATUS LOCK = 1? YES CONTINUE CONTINUE MC9S08GB60A Data Sheet, Rev MHz) Bus CHECK NO YES Freescale Semiconductor ...
Page 121
... ICGS2 = $xx This is read only; good idea to read this before performing time critical operations ICGFLTLU/L = $xx Not used in this example ICGTRM = $xx Bit 7:0 TRIM Freescale Semiconductor / 64, f IRG IRG Configures oscillator for low-power operation Configures oscillator for low-frequency range; FLL prescale factor is 64 Oscillator using crystal or resonator requested (bit is really a don’ ...
Page 122
... Many other possible trimming procedures are valid and can be used. 122 NO YES NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. MC9S08GB60A Data Sheet, Rev. 2 RECOVERY FROM STOP3 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Freescale Semiconductor ...
Page 123
... Refer to the direct-page register summary in address assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor START TRIM PROCEDURE ICGTRM = $80 MEASURE ...
Page 124
... Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. 124 5 4 REFS CLKS 0 0 Figure 7-12. ICG Control Register 1 (ICGC1) Table 7-6. ICGC1 Field Descriptions Description MC9S08GB60A Data Sheet, Rev OSCSTEN LOCD Freescale Semiconductor ...
Page 125
... Division Factor ( 001 Division Factor ( 010 Division Factor ( 011 Division Factor ( 100 Division Factor ( 101 Division Factor ( 110 Division Factor ( 111 Division Factor (R) = 128 Freescale Semiconductor 5 4 MFD LOCRE 0 0 Figure 7-13. ICG Control Register 2 (ICGC2) Table 7-7. ICGC2 Field Descriptions Description MC9S08GB60A Data Sheet, Rev ...
Page 126
... Writing ICGIF has no effect ICG interrupt request is pending ICG interrupt request is pending. 126 REFST LOLS LOCK Figure 7-14. ICG Status Register 1 (ICGS1) Table 7-8. ICGS1 Field Descriptions Description MC9S08GB60A Data Sheet, Rev ICG LOCS ERCS Freescale Semiconductor ...
Page 127
... FLT read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. Freescale Semiconductor ...
Page 128
... Increasing the binary value in TRIM will increase the period and decreasing the value will decrease the period. 128 FLT Table 7-11. ICGFLTL Field Descriptions Description TRIM Unaffected by MCU reset Figure 7-18. ICG Trim Register (ICGTRM) Table 7-12. ICGTRM Field Descriptions Description MC9S08GB60A Data Sheet, Rev Freescale Semiconductor ...
Page 129
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...
Page 130
... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents of X. 130 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-1. CPU Registers MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 131
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Chapter 8 Central Processor Unit (S08CPUV2) ...
Page 132
... No carry out of bit 7 1 Carry out of bit 7 132 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register Table 8-1. CCR Register Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 133
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Chapter 8 Central Processor Unit (S08CPUV2) ...
Page 134
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 134 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 135
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08GB60A Data Sheet, Rev. 2 ...
Page 136
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 136 chapter for more details. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 137
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Chapter 8 Central Processor Unit (S08CPUV2) ...
Page 138
... Condition code register (CCR) bits Two’s complement overflow indicator, bit Half carry, bit Interrupt mask, bit Negative indicator, bit Zero indicator, bit Carry/borrow, bit 0 (carry out of bit CCR activity notation Bit not affected – = 138 MC9S08GB60A Data Sheet, Rev. 2 Table 8-2. Freescale Semiconductor ...
Page 139
... Address modes Inherent (no operands) INH = 8-bit or 16-bit immediate IMM = 8-bit direct DIR = 16-bit extended EXT = Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Chapter 8 Central Processor Unit (S08CPUV2) 139 ...
Page 140
... IX1 SP2 9EDB ee ff SP1 9EEB IMM A4 ii DIR B4 dd EXT IX2 – IX1 SP2 9ED4 ee ff SP1 9EE4 ff DIR 38 dd INH 48 INH 58 – – IX1 SP1 9E68 ff DIR 37 dd INH 47 INH 57 – – IX1 SP1 9E67 Freescale Semiconductor ...
Page 141
... Branch if Interrupt Mask BMS rel Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always Freescale Semiconductor Description ← 0 – – – – – – – – – – – – Branch if ( – – – – – – Branch if ( Branch if (N ⊕ ...
Page 142
... INH 9A DIR 3F dd INH 4F INH 5F INH 8C IX1 SP1 9E6F ff IMM A1 ii DIR B1 dd EXT IX2 – – IX1 SP2 9ED1 ee ff SP1 9EE1 ff DIR 33 dd INH 43 INH 53 1 IX1 SP1 9E63 ff EXT IMM – – DIR 75 dd SP1 9EF3 ff Freescale Semiconductor ...
Page 143
... LDA oprx16,SP LDA oprx8,SP LDHX #opr16i LDHX opr8a LDHX opr16a Load Index Register (H:X) LDHX ,X from Memory LDHX oprx16,X LDHX oprx8,X LDHX oprx8,SP Freescale Semiconductor Description (X) – (M) (CCR Updated But Operands Not Changed) U – – (A) 10 Decrement Branch if (result) ≠ 0 – – – – – – ...
Page 144
... DIR 30 dd INH 40 INH 50 – – IX1 SP1 9E60 ff INH 9D INH 62 IMM AA ii DIR BA dd EXT IX2 – IX1 SP2 9EDA ee ff SP1 9EEA ff INH 87 INH 8B INH 89 INH 86 INH 8A INH 88 DIR 39 dd INH 49 INH 59 – – IX1 SP1 9E69 ff Freescale Semiconductor ...
Page 145
... SUB #opr8i SUB opr8a SUB opr16a SUB oprx16,X Subtract SUB oprx8,X SUB ,X SUB oprx16,SP SUB oprx8,SP SWI Software Interrupt Freescale Semiconductor Description ← 0xFF – – – – – – (High Byte Not Affected) SP ← (SP) + 0x0001; Pull (CCR) SP ← (SP) + 0x0001; Pull (A) SP ← ...
Page 146
... SP ← (H:X) – 0x0001 – – – – – – I bit ← 0; Halt CPU – – 0 – – – MC9S08GB60A Data Sheet, Rev. 2 Effect on CCR INH 84 INH 97 INH 85 DIR 3D dd INH 4D INH 5D – IX1 SP1 9E6D ff INH 95 INH 9F INH 94 INH 8F Freescale Semiconductor ...
Page 147
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 8-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 148
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 149
... Four falling-edge/low-level or rising-edge/high-level sensitive — Choice of edge-only or edge-and-level sensitivity — Common interrupt flag and interrupt enable control — Capable of waking up the MCU from stop3 or wait mode Freescale Semiconductor Connections” for more information about the logic and hardware aspects PTA6/ PTA5/ ...
Page 150
... SDA1 PTC2/SDA1 SCL1 PTC1/RxD2 SCL1 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 5 PTD4/TPM2CH1 PTD3/TPM2CH0 PTD2/TPM1CH2 3 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 SPSCK1 PTE5/SPSCK1 MOSI1 PTE4/MOSI1 MISO1 PTE3/MISO1 SS1 PTE2/SS1 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 8 PTF7–PTF0 4 PTG7–PTG4 PTG3 EXTAL PTG2/EXTAL XTAL PTG1/XTAL BKGD PTG0/BKGD/MS Freescale Semiconductor ...
Page 151
... Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor KBACK V RESET ...
Page 152
... Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = 0) 0 Edge-only detection 1 Edge-and-level detection 152 KBF KBEDG5 KBEDG4 Description MC9S08GB60A Data Sheet, Rev KBIE KBIMOD KBACK Freescale Semiconductor ...
Page 153
... When the MCU enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop mode. Freescale Semiconductor ...
Page 154
... When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard input is at its asserted level. 154 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 155
... Timer system enable • One interrupt per channel plus terminal count interrupt Freescale Semiconductor (Section 7.3.9, “Fixed Frequency MC9S08GB60A Data Sheet, Rev. 2 Clock”). Selecting XCLK as the clock 155 ...
Page 156
... SDA1 PTC2/SDA1 SCL1 PTC1/RxD2 SCL1 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 5 PTD4/TPM2CH1 PTD3/TPM2CH0 PTD2/TPM1CH2 3 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 SPSCK1 PTE5/SPSCK1 MOSI1 PTE4/MOSI1 MISO1 PTE3/MISO1 SS1 PTE2/SS1 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 8 PTF7–PTF0 4 PTG7–PTG4 PTG3 EXTAL PTG2/EXTAL XTAL PTG1/XTAL BKGD PTG0/BKGD/MS Freescale Semiconductor ...
Page 157
... TPMxCnVH:TPMxCnVL 16-BIT LATCH The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulo counter up-/down-counter when the TPM is configured for center-aligned PWM. The TPM Freescale Semiconductor Pins and Connections chapter for more information). CLOCK SOURCE PRESCALE AND SELECT ...
Page 158
... TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the 158 Pins and Connections MC9S08GB60A Data Sheet, Rev. 2 chapter for additional information Freescale Semiconductor ...
Page 159
... This corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.) Freescale Semiconductor Section 10.7.1, “Timer x Status and Control for more information about clock source selection. ...
Page 160
... TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value 160 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 161
... If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is $0001 through $7FFE ($7FFF if Freescale Semiconductor OVERFLOW PERIOD ...
Page 162
... Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 162 COUNT = 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT UP) (COUNT DOWN) PULSE WIDTH 2 x PERIOD 2 x MC9S08GB60A Data Sheet, Rev. 2 COUNT = TPMxMODH:TPMx Freescale Semiconductor ...
Page 163
... When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section 10.6.1, “Clearing Timer Interrupt Freescale Semiconductor chapter for absolute interrupt vector addresses, priority, and local Flags.” Flags.” ...
Page 164
... TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2. 164 Section 10.6.1, “Clearing Timer Interrupt Memory chapter of this data sheet for the absolute address MC9S08GB60A Data Sheet, Rev. 2 Flags.” Freescale Semiconductor ...
Page 165
... Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in PS[2:0] Table 10-3. This prescaler is located after any clock source synchronization or clock source selection affects whatever clock source is selected to drive the TPM system. Freescale Semiconductor CPWMS ...
Page 166
... Fixed system clock (XCLK) External source (TPMx Ext Clk) Table 10-3. Prescale Divisor Selection Any write to TPMxCNTH clears the 16-bit counter Any write to TPMxCNTL clears the 16-bit counter MC9S08GB60A Data Sheet, Rev TPM Clock Source Divided- 128 Freescale Semiconductor 0 Bit Bit 0 0 ...
Page 167
... It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. Freescale Semiconductor 5 4 ...
Page 168
... This is also the setting required for channel 0 when the TPMxCH0 pin is used as an external clock input. 168 MSnB MSnA ELSnB Description Table 10-5 Table 10-5, these bits select the polarity of the input edge that triggers an MC9S08GB60A Data Sheet, Rev ELSnA 0 0 Table 10-5. for a summary of channel mode and setup Freescale Semiconductor ...
Page 169
... R Bit Reset 0 0 Figure 10-12. Timer Channel Value Register Low (TPMxCnVL) Freescale Semiconductor Mode Pin not used for TPM channel; use as an external clock for the TPM or 00 revert to general-purpose I/O 01 Capture on rising edge only 10 Input capture Capture on falling edge only ...
Page 170
... When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 170 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 171
... This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 171 ...
Page 172
... SDA1 PTC2/SDA1 SCL1 PTC1/RxD2 SCL1 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 5 PTD4/TPM2CH1 PTD3/TPM2CH0 PTD2/TPM1CH2 3 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 SPSCK1 PTE5/SPSCK1 MOSI1 PTE4/MOSI1 MISO1 PTE3/MISO1 SS1 PTE2/SS1 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 8 PTF7–PTF0 4 PTG7–PTG4 PTG3 EXTAL PTG2/EXTAL XTAL PTG1/XTAL BKGD PTG0/BKGD/MS Freescale Semiconductor ...
Page 173
... Section 11.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop modes Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Serial Communications Interface (S08SCIV1) 173 ...
Page 174
... TRANSMIT CONTROL TDRE TIE TC TCIE Figure 11-2. SCI Transmitter Block Diagram MC9S08GB60A Data Sheet, Rev. 2 shows the receiver portion of the SCI.) LOOPS RSRC LOOP TO RECEIVE CONTROL DATA IN TO TxD PIN SCI CONTROLS TxD TO TxD PIN LOGIC TxD DIRECTION Tx INTERRUPT REQUEST Freescale Semiconductor ...
Page 175
... SCI. INTERNAL BUS 16 × BAUD RATE CLOCK FROM RxD PIN DATA RECOVERY LOOPS SINGLE-WIRE LOOP CONTROL RSRC FROM TRANSMITTER PE PT Freescale Semiconductor (READ-ONLY) SCID – Rx BUFFER DIVIDE 11-BIT RECEIVE SHIFT REGISTER WAKE WAKEUP LOGIC ILT RDRF ...
Page 176
... When 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in 176 Memory chapter of this data sheet for the absolute address SBR12 SBR11 Description SBR5 SBR4 SBR3 Description MC9S08GB60A Data Sheet, Rev SBR10 SBR9 SBR8 Table 11- SBR2 SBR1 SBR0 Table 11-1. Freescale Semiconductor ...
Page 177
... Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total PT number the data character, including the parity bit, is odd. Even parity means the total number the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. Freescale Semiconductor RSRC M ...
Page 178
... Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin LOOPS = 1 , the RxD pin reverts to being a general-purpose I/O pin even Receiver off. 1 Receiver on. 178 RIE ILIE Description Idle,” for more details. MC9S08GB60A Data Sheet, Rev RWU SBK Freescale Semiconductor ...
Page 179
... TC is cleared automatically by reading SCIxS1 with and then doing one of the following three things: • Write to the SCI data register (SCIxD) to transmit new data • Queue a preamble by changing TE from • Queue a break character by writing 1 to SBK in SCIxC2 Freescale Semiconductor Description Section 11.3.3.2, “Receiver Wakeup Section 11.3.2.1, “Send Break and Queued ...
Page 180
... Parity Error Flag — set at the same time as RDRF when parity is enabled ( and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD parity error. 1 Parity error. 180 Description MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 181
... SCIxD is written. 5 TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation TXDIR (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. Freescale Semiconductor Figure 11-9 ...
Page 182
... Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags Reset 0 0 182 Description Figure 11-11. SCI Data Register (SCIxD) MC9S08GB60A Data Sheet, Rev Freescale Semiconductor ...
Page 183
... For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ± ...
Page 184
... This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received all eight data bits and a framing error ( occurs. ...
Page 185
... At the end of a message the beginning of the next message, all receivers automatically force RWU all receivers wake up in time to look at the first character(s) of the next message. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Serial Communications Interface (S08SCIV1) Section 11 ...
Page 186
... TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD. 186 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 187
... Because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Serial Communications Interface (S08SCIV1) ...
Page 188
... TxD1 pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD1 pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. 188 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 189
... SPI functionality are shared with port E pins 2–5. See the Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as general-purpose I/O. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 2 Appendix A, “Electrical 189 ...
Page 190
... SDA1 PTC2/SDA1 SCL1 PTC1/RxD2 SCL1 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 5 PTD4/TPM2CH1 PTD3/TPM2CH0 PTD2/TPM1CH2 3 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 SPSCK1 PTE5/SPSCK1 MOSI1 PTE4/MOSI1 MISO1 PTE3/MISO1 SS1 PTE2/SS1 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 8 PTF7–PTF0 4 PTG7–PTG4 PTG3 EXTAL PTG2/EXTAL XTAL PTG1/XTAL BKGD PTG0/BKGD/MS Freescale Semiconductor ...
Page 191
... In this system, the master device has configured its SS pin as an optional slave select output. MASTER SPI SHIFTER CLOCK GENERATOR Freescale Semiconductor MOSI MOSI MISO MISO SPSCK SPSCK SS SS Figure 12-2. SPI System Connections MC9S08GB60A Data Sheet, Rev. 2 Serial Peripheral Interface (S08SPIV3) SLAVE SPI SHIFTER ...
Page 192
... MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. 192 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 193
... SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. Freescale Semiconductor Tx BUFFER (WRITE SPI1D) SHIFT SPI SHIFT REGISTER ...
Page 194
... PRESCALER CLOCK RATE DIVIDER DIVIDE 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure 12-4. SPI Baud Rate Generation MC9S08GB60A Data Sheet, Rev. 2 MASTER DIVIDE BY SPI BIT RATE Freescale Semiconductor ...
Page 195
... SPI system enabled 5 SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested Freescale Semiconductor Memory chapter of this data sheet for the absolute address ...
Page 196
... General-purpose I/O (not SPI) General-purpose I/O (not SPI) SS input for mode fault Automatic SS output NOTE MODFEN BIDIROE MC9S08GB60A Data Sheet, Rev. 2 Table 12-2. Slave Mode Slave select input Slave select input Slave select input Slave select input SPISWAI SPC0 Freescale Semiconductor ...
Page 197
... SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in SPR[2:0] Table 12-6. The input to this divider comes from the SPI baud rate prescaler (see divider is the SPI bit rate clock for master mode. Freescale Semiconductor Description ...
Page 198
... Table 12-6. SPI Baud Rate Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1 SPTEF MODF 1 0 Figure 12-8. SPI Status Register (SPI1S) MC9S08GB60A Data Sheet, Rev Rate Divisor 128 256 Freescale Semiconductor ...
Page 199
... Data may be read from SPI1D any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. Freescale Semiconductor Description 5 ...
Page 200
... LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the 200 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor ...