MC9S08GB60ACFUE Freescale Semiconductor, MC9S08GB60ACFUE Datasheet - Page 91

• Manufacturer Part Number: MC9S08GB60ACFUE
• Description: IC MCU 60K FLASH 4K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GB60ACFUE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: S08GB
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 8
• Operating Supply Voltage: 0 V to 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.6.2
Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as
general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable
(PTBPE), and slew rate control (PTBSE) registers.
If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored.
When a port B pin is being used as an ATD pin, reads of PTBD will return a 0 of the corresponding pin,
provided PTBDD is 0.
Freescale Semiconductor
PTBPE[7:0]
PTBD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTBPE7
PTBD7
Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD)
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and the
internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
0
0
7
7
PTBPE6
PTBD6
0
0
6
6
Figure 6-14. Pullup Enable for Port B (PTBPE)
Figure 6-13. Port B Data Register (PTBD)
Table 6-6. PTBPE Field Descriptions
PTBPE5
Table 6-5. PTBD Field Descriptions
PTBD5
MC9S08GB60A Data Sheet, Rev. 2
0
0
5
5
PTBPE4
PTBD4
0
0
4
4
Description
Description
PTBPE3
PTBD3
3
0
3
0
PTBPE2
PTBD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTBPE1
PTBD1
0
0
1
1
PTBPE0
PTBD0
0
0
0
0
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