MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 482

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (S08ADC16)
The ADC module has the capability of automatically averaging the result of multiple conversions. The
hardware average function is enabled by setting the AVGE bit and operates with any of the conversion
modes and configurations.
21.5.1
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC may not perform according to specifications. If the available clocks
are too fast, the clock must be divided to the appropriate frequency. This divider is specified by the ADIV
bits and can be divide-by 1, 2, 4, or 8.
21.5.2
The pin control registers (APCTL1, APCTL2, APCTL3, and APCTL4) disable the I/O port control of the
pins used as analog inputs.When a pin control register bit is set, the following conditions are forced for the
associated MCU pin:
21.5.3
The ADC can be configured to accept one of three voltage reference pairs as the reference voltage (V
and V
minimum Ref Voltage High (defined in Appendix A) and V
at the same potential as V
V
REFSEL bits in the ADCSC2 register.The alternate (V
additional external pins or internal sources depending on MCU configuration.Consult the module
introduction for information on the Voltage References specific to this MCU.
21-26
ALTL
•
•
•
•
•
•
•
REFSL
) and the internal bandgap (V
The bus clock, which is equal to the frequency at which software is executed. This is the default
selection following reset.
The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of
the bus clock with using the ADIV bits.
ALTCLK, as defined for this MCU (See module section introduction).
The asynchronous clock (ADACK). This clock is generated from a clock source within the ADC
module. Conversions are possible using ADACK as the input clock source while the MCU is in
stop3 mode. Refer to
The output buffer is forced to its high impedance state.
The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
The pullup is disabled.
Clock Select and Divide Control
Input Select and Pin Control
Voltage Reference Selection
) used for conversions. Each pair contains a positive reference which must be between the
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
SSAD
Section 21.5.5.4
. The three pairs are external (V
BGH
and V
for more information.
BGL
). These voltage references are selected using the
ALTH
DDAD
and V
REFH
, and a ground reference which must be
ALTL
and V
) voltage reference pair may select
REFL
), alternate (V
Freescale Semiconductor
ALTH
REFSH
and