MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 508

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Programmable Delay Block (PDB)
22.2.2.5
This register contains status and control bits for the channel n of the Programmable Delay Block. The
channel outputs are enabled if either ENA or ENB have been set to one.
22-8
RESERVED
RESET:
ERRA
ERRB
W
Field
R
AOS
BOS
13:6
ENA
ENB
5:4
3:2
15
14
1
0
ERR
15
A
0
Figure 22-7. Programmable Delay Block Channel n Control Register (PDBCHnCR)
Sequence error on TriggerA
0 = No sequence error on TriggerA
1 = Sequence error is detected on TriggerA. The Delay A is timed out before the previous ADC conversion, which
is triggered by TriggerB, is done.
A PDB sequence error interrupt is generated when this bit is set. Write 1 clear this bit.
Sequence error on TriggerB
0 = No sequence error on TriggerB
1 = Sequence error is detected on TriggerB. The Delay B is timed out before the previous ADC conversion, which
is triggered by TriggerA, is done.
A PDB sequence error interrupt is generated when this bit is set. Write 1 clear this bit.
RESERVED. Write these register bits as zero.
Channel n TriggerA Output Select
00 = Counter delay is bypassed
01 = TriggerA is function of Delay A
10 = Reserved
11 = Reserved
Channel n TriggerB Output Select
00 = Counter delay is bypassed
01 = TriggerB is function of Delay B
10 = Reserved
11 = Reserved
TriggerA Enable
0 = PreTriggerA and TriggerA outputs are disabled (and forced to zero)
1 = PreTriggerA and TriggerA outputs are enabled
TriggerB Enable
0 = PreTriggerB and TriggerB outputs are disabled (and forced to zero)
1 = PreTriggerB and TriggerB outputs are enabled
PDB Channel n Control Register (PDBCHnCR)
ERR
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
14
B
0
= Reserved or unused
13
0
Table 22-3. PDBCHnCR Register Field Descriptions
12
0
11
0
RESERVED
10
0
9
0
Description
8
0
7
0
6
0
5
0
AOS
4
0
3
0
Freescale Semiconductor
BOS
2
0
ENA
1
0
ENB
0
0