MC68CK16Z1CAG16 Freescale Semiconductor, MC68CK16Z1CAG16 Datasheet - Page 382

• Manufacturer Part Number: MC68CK16Z1CAG16
• Description: IC MICROPROCESSOR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68CK16Z1CAG16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 144LQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

W — Frequency Control (VCO)
X — Frequency Control (Prescaler)
Y[5:0] — Frequency Control (Counter)
EDIV — E Clock Divide Rate
SLOCK — Synthesizer Lock Flag
STSIM — Stop Mode SIM Clock
STEXT — Stop Mode External Clock
D.2.4 Reset Status Register
RSR — Reset Status Register
EXT — External Reset
D-8
15
This bit controls a prescaler tap in the synthesizer feedback loop. Setting this bit in-
creases the VCO speed by a factor of four. VCO relock delay is required.
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop.
Setting the bit doubles clock speed without changing the VCO speed. No VCO relock
delay is required.
The Y field controls the modulus down counter in the synthesizer feedback loop, caus-
ing it to divide by a value of Y + 1. VCO relock delay is required.
The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate
synthesizer lock status until after the user first writes to SYNCR.
RSR contains a status bit for each reset source in the MCU. RSR is updated when the
MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple
sources assert reset signals at the same time, more than one bit in RSR may be set.
This register can be read at any time; a write has no effect. Bits [15:8] are unimple-
mented and always read zero.
Reset caused by the RESET pin.
0 = ECLK frequency is system clock divided by eight.
1 = ECLK frequency is system clock divided by sixteen.
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency or VCO is disabled.
0 = When LPSTOP is executed, the SIM clock is driven from the external crystal
1 = When LPSTOP is executed, the SIM clock is driven from the internal VCO.
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve
1 = When LPSTOP is executed and EXOFF 1 in SIMCR, the CLKOUT signal is
oscillator and the VCO is turned off to conserve power.
power.
driven from the SIM clock, as determined by the state of the STSIM bit.
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
REGISTER SUMMARY
8
EXT
7
POW
6
SW
5
HLT
4
3
0
M68HC16 Z SERIES
RSVD
USER’S MANUAL
2
$YFFA06
SYS
1
TST
0