C8051F063-GQR Silicon Laboratories Inc, C8051F063-GQR Datasheet - Page 215

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C8051F063-GQR

Manufacturer Part Number
C8051F063-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Datasheets

Specifications of C8051F063-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN, I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F060DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit, 1 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1214 - DEV KIT FOR F060/F062/F063
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F063-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Bits7-0:
Note:
Bits7-0:
P1.7
R/W
R/W
Bit7
Bit7
P1.[7:0]: Port1 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
On the C8051F060/1/2/3, P1.[7:0] can be configured as inputs to ADC2 as AIN2.[7:0], in
which case they are ‘skipped’ by the Crossbar assignment process and their digital input
paths are disabled, depending on P1MDIN (See Figure 18.12). Note that in analog mode,
the output mode of the pin is determined by the Port 1 latch and P1MDOUT (Figure 18.13).
See
about ADC2.
P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pull-up on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. The state of the weak pull-up is determined by the WEAKPUD bit (XBR2.7,
see Figure 18.7).
Section “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page 87
P1.6
R/W
R/W
Bit6
Bit6
Figure 18.12. P1MDIN: Port1 Input Mode Register
P1.5
R/W
R/W
Bit5
Bit5
Figure 18.11. P1: Port1 Data Register
P1.4
R/W
R/W
Bit4
Bit4
Rev. 1.2
P1.3
R/W
R/W
Bit3
Bit3
C8051F060/1/2/3/4/5/6/7
P1.2
R/W
R/W
Bit2
Bit2
P1.1
R/W
R/W
Bit1
Bit1
for more information
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P1.0
R/W
R/W
Bit0
Bit0
0x90
All Pages
0xAD
F
Addressable
Reset Value
Reset Value
11111111
11111111
Bit
215

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