C8051F063-GQR Silicon Laboratories Inc, C8051F063-GQR Datasheet - Page 76

• Manufacturer Part Number: C8051F063-GQR
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F063-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F060/1/2/3/4/5/6/7
6.2.
DMA instructions can request single-ended data from both ADC0 and ADC1, as well as the differential
combination of the two ADC inputs. The instruction format is identical to the DMA0IDT register, shown in
Figure 6.7. Depending on which bits are set to ‘1’ in the instruction word, either 2 or 4 bytes of data will be
written to XRAM for each DMA instruction cycle (excluding End-Of-Operation instructions). Table 6.1
details all of the valid DMA instructions. Instructions not listed in the table are not valid DMA instructions,
and should not be used. Note that the ADCs can be independently controlled by the microcontroller when
their outputs are not requested by the DMA.
6.3.
The DMA Interface can be configured to access either on-chip or off-chip XRAM. Any writes to on-chip
XRAM by the DMA Control Logic occur when the processor core is not accessing the on-chip XRAM. This
ensures that the DMA will not interfere with processor instruction timing.
Off-chip XRAM access (only available on the C8051F060/2/4/6) is controlled by the DMA0HLT bit in
DMA0CF (DMA Configuration Register, Figure 6.5). The DMA will have full access to off-chip XRAM when
this bit is ‘0’, and the processor core will have full access to off-chip XRAM when this bit is ‘1’. The
DMA0HLT bit should be controlled in software when both the processor core and the DMA Interface
require access to off-chip XRAM data space. Before setting DMA0HLT to ‘1’, the software should check the
DMA0XBY bit to ensure that the DMA is not currently accessing off-chip XRAM. The processor core can-
not access off-chip XRAM while DMA0HLT is ‘0’. The processor will continue as though it was able to per-
form the desired memory access, but the data will not be written to or read from off-chip XRAM. When the
processor core is finished accessing off-chip XRAM, DMA0HLT should be set back to ‘0’in software to
return control to the DMA Interface. The DMA Control Logic will wait until DMA0HLT is ‘0’ before writing
data to off-chip XRAM. If new data becomes available to the DMA Interface before the previous data has
been written, an overflow condition will occur, and the new data word may be lost.
The Data Address Pointer Registers (DMA0DSH and DMA0DSL) contain the 16-bit XRAM address loca-
tion where the DMA interface will write data. When the DMA is initially enabled, the DMA Data Address
76
Instruction
Word
00000000b End-Of-Operation
10000000b End-Of-Operation with Continuous Conversion
x0010000b Retrieve ADC0 Data
x0100000b Retrieve ADC1 Data
x0110000b Retrieve ADC0 and ADC1 Data
x10x0000b Retrieve Differential Data
x11x0000b
DMA0 Instruction Format
XRAM Addressing and Setup
Description
Retrieve Differential and ADC1 Data
Table 6.1. DMA0 Instruction Set
Rev. 1.2
to XRAM (2 bytes)
First Data Written
(differential result
(differential result
from both ADCs)
from both ADCs)
ADC0H:ADC0L
ADC1H:ADC1L
ADC0H:ADC0L
ADC0H:ADC0L
ADC0H:ADC0L
none
none
Written to XRAM
ADC1H:ADC1L
ADC1H:ADC1L
Second Data
(2 bytes)
none
none
none
none
none