HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 121

• Manufacturer Part Number: HD6417020SVX12IV
• Description: MCU 3/5V 0K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.2.3
Wait state control register 2 is a 16-bit read/write register that controls the number of states for
accessing each area with a DMA single address mode transfer and whether wait states are used.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by the
standby mode.
•
Bits 15–8 (wait state control during single-mode DMA transfer (DRW7–DRW0)): DRW7–
DRW0 determine the number of states in single-mode DMA memory read cycles for each area
and whether or not to sample the WAIT signal. Bits DRW7–DRW0 correspond to areas 7–0,
respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-mode
DMA memory read cycle for the corresponding area. If it is set to 1, sampling takes place.
For the external memory spaces of areas 1, 3–5, and 7, single-mode DMA memory read cycles
are completed in one state when the corresponding bits are cleared to 0. When they are set to 1,
the number of wait states is 2 plus the wait states from the WAIT signal. For the external
memory space of areas 0, 2, and 6, single-mode DMA memory read cycles are completed in
one state plus the long wait state number (set in wait state controller 3 (WCR3)) when the
corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 1 plus
the long wait state; when the WAIT signal is at low level as well, a wait state is inserted.
The DRAM space (area 1) finishes the column address output cycle in one state (short pitch)
when the DRW1 bit is 0, and in 2 states plus the wait states from the WAIT signal (long pitch)
when DRW1 is 1. The single-mode DMA memory read cycle of the address/data multiplexed
I/O space (area 6) is 4 states plus the wait states from the WAIT signal, regardless of the
setting of the DRW6 bit.
Table 8.4 summarizes single-mode DMA memory read cycle state information.
Initial value:
Initial value:
Bit name:
Bit name:
Wait State Control Register 2 (WCR2)
R/W:
R/W:
Bit:
Bit:
DWW7
DRW7
R/W
R/W
15
1
7
1
DWW6
DRW6
R/W
R/W
14
1
6
1
DWW5
DRW5
R/W
R/W
13
1
5
1
DWW4
DRW4
R/W
R/W
12
1
4
1
DWW3
DRW3
R/W
R/W
11
1
3
1
DWW2
DRW2
R/W
R/W
10
1
2
1
DWW1
DRW1
R/W
R/W
RENESAS 101
9
1
1
1
DWW0
DRW0
R/W
R/W
8
1
0
1