HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 91

• Manufacturer Part Number: HD6417020SVX12IV
• Description: MCU 3/5V 0K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.4
5.4.1
The sequence of interrupt operations will be explained below. Figure 5.2 is a flowchart of the
operations up to acceptance of the interrupt.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt in the interrupt requests sent,
3. The interrupt controller compares the priority level of the selected interrupt request with the
4. When the interrupt controller accepts an interrupt request, it drives the pin IRQOUT low.
5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the
6. In interrupt exception processing, first SR and PC are pushed onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3–I0) in
8. When the accepted interrupt is level-sensed or from an on-chip peripheral module, The pin
9. The CPU accesses the exception vector table at the entry for the vector number of the accepted
Note: A request for an external interrupt (IRQ) designated as edge-detected is held pending once
70 RENESAS
following the priority order indicated in table 5.3 and the levels set in interrupt priority
registers A–E (IPRA–IPRE). Lower priority interrupts are ignored*. If two interrupts with the
same priority level are requested simultaneously or if there are multiple interrupts occurring
within a single module, the interrupt with the highest default priority or priority within module
as indicated in table 5.3 is selected.
interrupt mask level bits (I3–I0) in the CPU’s status register (SR). If the request priority level
is equal to or less than the interrupt mask level, the request is ignored. If the request priority
level is higher than the interrupt mask level, the interrupt controller accepts the request and
sends an interrupt request signal to the CPU.
next instruction to be executed. Instead of executing that instruction, the CPU starts interrupt
exception processing.
the status register (SR).
IRQOUT returns to the high level. If the accepted interrupt is edge-sensed, the pin IRQOUT
returns to the high level when the instruction to be executed by the CPU in (5) is replaced by
the interrupt exception processing. If the interrupt controller has accepted another interrupt (of
a level higher than the current interrupt), however, the pin IRQOUT remains low.
interrupt, reads the start address of the exception service routine, branches to that address, and
starts executing the program there. This branch is not delayed.
only. An external interrupt designated as level-detected is held pending as long as the
interrupt request continues, but if the request is cleared before the CPU next accepts an
interrupt, the interrupt request is regarded as not having been made.
Interrupt requests from on-chip supporting modules are level requests. When the status
flag in a particular module is set, an interrupt is requested. For details, see the descriptions
of the individual modules. Note that the interrupt request will be continued unless an
Interrupt Operation
Interrupt Sequence