HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 159
![MCU 3/5V 0K PB-FREE 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
HD6417020SVX12IV
Manufacturer Part Number
HD6417020SVX12IV
Description
MCU 3/5V 0K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12IV
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417020SVX12IV
Manufacturer:
RENESAS
Quantity:
63
Company:
Part Number:
HD6417020SVX12IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait
states inserted into the DRAM access cycle can be controlled by setting WCR1 and WCR2. When
the corresponding bits in WCR1 and WCR2 are cleared to 0, the column address output cycle ends
in 1 state and no wait states are inserted. When the bit is 1, the WAIT pin input signal is sampled
on the rise of the system clock (CK) directly preceding the second state of the column address
output cycle and the wait state is inserted as long as the level is low. When a high level is detected,
it shifts to the second state. Figure 8.20 shows the wait state timing in a long pitch bus cycle.
A21–A0
A21–A0
WAIT
RAS
CAS
RAS
CAS
CK
CK
Figure 8.20 Wait State Timing during DRAM Access (Long Pitch)
T
T
p
p
1
Figure 8.19 Precharge Timing (Long Pitch)
Row address
T
T
p
r
2
T
Row address
T
c
r
1
T
cw
Column address
(wait state)
T
c
1
Column address
T
T
c
c
2
2
RENESAS 139
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