HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 403
HD6417020SVX12IV
Manufacturer Part Number
HD6417020SVX12IV
Description
MCU 3/5V 0K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12IV
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
4. After the end of serial transmission, the SCK pin is held in the high state.
Transmitting and Receiving Data: SCI Initialization (clocked synchronous mode): Before
transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register
(SCR), then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Figure 13.16 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI
is listed below.
RENESAS 386
Serial clock
Serial data
is selected, the SCI outputs data in synchronization with the input clock. Data are output from
the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
data from the TDR into the TSR, transmits the MSB, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, transmits the MSB, then
holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit
(TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
TDRE
TEND
Transmit direction
request
TXI
Figure 13.15 Example of SCI Transmit Operation
Bit 0
LSB
clears TDRE to 0
data in TDR and
handler writes
TXI interrupt
Bit 1
1 frame
request
TXI
MSB
Bit 7
Bit 0
Bit 1
Bit 6
request
TEI
Bit 7
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