M30280F6HP#U7B Renesas Electronics America, M30280F6HP#U7B Datasheet - Page 183

• Manufacturer Part Number: M30280F6HP#U7B
• Description: IC M16C/28 MCU FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#U7B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
1
e
E
. v
6
J
Table 13.10 SR Waveform Output Mode Specifications
Waveform output start condition
Waveform output stop condition
Interrupt request
OUTC1j pin
Selectable function
NOTES:
Output waveform
C
13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode
0
2
9
2 /
Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRi (i=0 to 7) is
set to "0" (output is not reversed) and the base timer value matches the G1POj register value (j=0, 2, 4, 6).
The "H" signal switches to a low-level ("L") signal when the base timer value matches the G1POk(k=j+1)
register value. Table 13.10 lists specifications of SR waveform mode. Figure 13.24 shows an example of
the SR waveform mode operation.
2. When the G1PO0 register resets the base timer, the channel 0 and channel 1 SR waveform generating functions
0 .
1. The odd channel's waveform generating register must have greater value than the even channel's.
3. The OUTC1
B
8
0
0
are not available.
0
G
4
J
7
a
o r
0 -
. n
u
2
p
3
(3)
Item
0
, 1
0
(
M
2
1
0
0
, OUTC1
0
6
7
C
2 /
page 161
, 8
M
2
, OUTC14, OUTC1
1
6
C
(3)
2 /
f o
8
3
• Free-running operation
• The base timer is cleared to "0000
Bits IFEj and IFEk in the G1FE register is set to "1" (channel j function enabled)
Bits IFEj and IFEk are set to "0" (channel j function disabled)
The G1IRj bit in the G1IR register is set to "1" when the base timer value
matches the G1POj register value.
The G1IRk bit in the interrupt request register is set to "1 " when the base
timer value matches the G1POk register value (See Figure 13.24)
Pulse signal output pin
• Default value set function : Set starting waveform output level
• Inverse output function : Waveform output signal is inversed and provided
) B
8
Cycle
(a) G1PO0 register (enabled by setting RST1 bit to "1", and RST4 and RST2 bits to "0")
(b) G1BTRR register (enabled by setting RST4 bit to "1", and RST2 and RST1 bits to "0")
(the RST1, RTS2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to "0" (no reset))
Inverse level width
following register
Cycle
Inverse level width
from the OUTC1j pin
5
m : setting value of the G1POj register (j=0, 2, 4, 6 )
n : setting value of the G1POk register (k=j+1)
p : setting value of the G1PO0 register or G1BTRR register
value range of m, n, p: 0001
6
pins.
(1)
(1)
:
:
:
:
65536
p+2
n-m
n-m
f
f
f
f
BT1
BT1
BT1
BT1
Specification
16
16
" by matching the base timer with either
to FFFD
16
13. Timer S
(2)
, or