M30280F6HP#U7B Renesas Electronics America, M30280F6HP#U7B Datasheet - Page 215

• Manufacturer Part Number: M30280F6HP#U7B
• Description: IC M16C/28 MCU FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#U7B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
1
e
E
Table 14.11 Registers to Be Used and Settings in I
. v
6
NOTES:
J
Register
U2TB
U2RB
U2BRG 0 to 7
U2MR
U2C0
U2C1
U2SMR IICM
U2SMR2 IICM2
U2SMR3 0, 2, 4 and NODC Set to “0”
0
C
2
9
2 /
1. Not all bits in the register are described above. Set those bits to “0” when writing to the registers in I
0 .
B
8
0
0
0
(1)
G
(1)
4
J
7
a
o r
0 -
. n
0 to 7
0 to 7
8
ABT
OER
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
ABC
BBS
3 to 7
CSC
SWC
ALS
STAC
SWC2
SDHI
7
CKPH
DL2 to DL0
u
2
p
3
0
, 1
0
(
M
2
1
0
Bit
0
6
7
C
2 /
, 8
page 193
M
1
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to ‘010
Set to “0”
Set to “0”
Select the count source for the U2BRG
register
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Set to “1”
Select the timing at which arbitration-lost Invalid
is detected
Bus busy flag
Set to “0”
Refer to Table 14.13
Set this bit to “1” to enable clock
synchronization
Set this bit to “1” to have SCL
fixed to “L” at the falling edge of the 9th
bit of clock
Set this bit to “1” to have SDA
stopped when arbitration-lost is detected
Set to “0”
Set this bit to “1” to have SCL
forcibly pulled low
Set this bit to “1” to disable SDA
Set to “0”
Refer to Table 14.13
Set the amount of SDA
6
C
2 /
f o
8
3
) B
8
5
2
’
Master
2
digital delay
2
2
2
2
C bus mode (1) (Continued)
output
output
output
2
output
Function
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to ‘010
Set to “1”
Set to “0”
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Set to “1”
Bus busy flag
Set to “0”
Refer to Table 14.13
Set to “0”
Set this bit to “1” to have SCL
fixed to “L” at the falling edge of the 9
bit of clock
Set to “0”
Set this bit to “1” to initialize UART2 at
start condition detection
Set this bit to “1” to have SCL
forcibly pulled low
Set this bit to “1” to disable SDA
Set to “0”
Set to “0”
Refer to Table 14.13
Set the amount of SDA
2
’
Slave
2
digital delay
2
2
2
C bus mode.
output
output
14. Serial I/O
2
output
th