MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 130

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.4 System Protection
5.4.1 Reset Status
5.4.2 Bus Monitor
5-24
The system protection block preserves reset status, monitors internal activity, and pro-
vides periodic interrupt generation.
The reset status register (RSR) latches internal MCU status during reset. Refer to
5.7.10 Reset Status Register
The internal bus monitor checks data size acknowledge (DSACK) or autovector
(AVEC) signal response times during normal bus cycles. The monitor asserts the in-
ternal bus error (BERR) signal when the response time is excessively long.
DSACK and AVEC response times are measured in clock cycles. Maximum allowable
response time can be selected by setting the bus monitor timing (BMT[1:0]) field in the
system protection control register (SYPCR).
CLOCK
2
9
PRESCALER
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5-8 System Protection
SYSTEM INTEGRATION MODULE
SPURIOUS INTERRUPT MONITOR
Go to: www.freescale.com
MODULE CONFIGURATION
for more information.
RESET STATUS
HALT MONITOR
BUS MONITOR
AND TEST
Figure 5-8
SOFTWARE WATCHDOG TIMER
PERIODIC INTERRUPT TIMER
Table 5-8
is a block diagram of the submodule.
shows the periods allowed.
M68HC16 Z SERIES
RESET REQUEST
BERR
RESET REQUEST
IRQ[7:1]
USER’S MANUAL
SYS PROTECT BLOCK