MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 273

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

M68HC16 Z SERIES
USER’S MANUAL
In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler
outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are pro-
vided. Connected to these outputs are two multiplexers, one for the capture/compare
unit, the other for the PWM unit.
Multiplexers can each select one of seven prescaler taps or an external input from the
PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0]
in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter
(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC). After re-
set, the GPT is configured to use system clock divided by four for TCNT and system
clock divided by two for PWMCNT. Initialization software can change the division fac-
tor. The PPR bits can be written at any time, but the CPR bits can only be written once
after reset, unless the GPT is in test or freeze mode.
PCLK
PIN
SYSTEM CLOCK
Freescale Semiconductor, Inc.
DIVIDER
Figure 11-2 Prescaler Block Diagram
For More Information On This Product,
SYNCHRONIZER AND
DIGITAL FILTER
GENERAL-PURPOSE TIMER
Go to: www.freescale.com
256
128
128
EXT.
EXT.
64
32
16
64
32
16
8
4
8
4
2
CPR2 CPR1 CPR0
PPR2 PPR1 PPR0
512
EXT.
SELECT
SELECT
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
TO CAPTURE/
PWM UNIT
COMPARE
TIMER
TO
GPT PRE BLOCK
11-9