MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 430

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

D.7.4 MCCI Interrupt Vector Register
MIVR — MCCI Interrupt Vector Register
The MIVR determines which three vectors in the exception vector table are to be used for
MCCI interrupts. The SPI and both SCI interfaces have separate interrupt vectors adja-
cent to one another. When initializing the MCCI, program INTV[7:2] so that INTV[7:0] cor-
respond to three of the user-defined vectors ($40–$FF). INTV[1:0] are determined by the
serial interface causing the interrupt, and are set by the MCCI.
At reset, MIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector
in the exception table.
INTV[7:2] — Interrupt Vector
INTV[1:0] — Interrupt Vector Source
D.7.5 SPI Interrupt Level Register
ILSPI — SPI Interrupt Level Register
The ILSPI determines the priority level of interrupts requested by the SPI.
Bits [15:14] — Not Implemented
D-56
15
15
NOT USED
RESET:
RESET:
INTV[7:2] are the six high-order bits of the three MCCI interrupt vectors for the MCCI,
as programmed by the user.
INTV[1:0] are the two low-order bits of the three interrupt vectors for the MCCI. They
are automatically set by the MCCI to indicate the source of the interrupt. Refer to
D-38.
Writes to INTV0 and INTV1 have no meaning or effect. Reads of INTV0 and INTV1
return a value of one.
14
14
13
13
0
ILSPI[2:0]
12
12
0
ILSCI
Freescale Semiconductor, Inc.
11
11
0
Table D-38 Interrupt Vector Sources
For More Information On This Product,
INTV[1:0]
10
10
00
01
10
NOT USED
Go to: www.freescale.com
REGISTER SUMMARY
9
9
8
8
Source of Interrupt
7
0
7
SCIA
SCIB
SPI
6
0
6
5
0
5
INTV[7:2]
NOT USED
4
0
4
3
1
3
M68HC16 Z SERIES
USER’S MANUAL
2
1
2
$YFFC05
$YFFC06
1
1
1
INTV[1:0]
Table
0
1
0