MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 61

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

SPCR2 — QSPI Control Register 2
SPIFIE — SPI Finished Interrupt Enable
WREN — Wrap Enable
WRTO — Wrap To
Bit 12 — Not Implemented
ENDQP — Ending Queue Pointer
Bits [7:4] — Not Implemented
NEWQP — New Queue Pointer Value
SPCR3 — QSPI Control Register 3
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
HMIE — HALTA and MODF Interrupt Enable
MC68331TS/D
RESET:
RESET:
SPIFIE
15
15
0
0
0
SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM
has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit value while
the QSPI is operating is ineffective on the current serial transfer, but becomes effective on the next se-
rial transfer. Reads of SPCR2 return the current value of the register, not of the buffer.
SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag SPIF.
WREN enables or disables wraparound mode.
When wraparound mode is enabled, after the end of queue has been reached, WRTO determines
which address the QSPI executes.
This field contains the last QSPI queue address.
This field contains the first QSPI queue address.
SPCR3 contains QSPI configuration parameters. The CPU can read and write SPCR3, but the QSM
has read-only access.
LOOPQ controls feedback on the data serializer for testing.
HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR.
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
0 = Wraparound mode disabled
1 = Wraparound mode enabled
0 = Feedback path disabled
1 = Feedback path enabled
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
WREN
14
14
0
0
0
WRTO
13
13
0
0
0
12
12
0
0
0
0
Freescale Semiconductor, Inc.
11
11
For More Information On This Product,
0
0
0
LOOPQ
10
0
0
ENDQP
Go to: www.freescale.com
HMIE
0
9
0
HALT
8
0
8
0
7
0
0
7
6
0
0
5
0
0
4
0
0
SPSR
3
0
0
NEWQP
$YFFC1C
$YFFC1E
0
0
0
0
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