MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 67

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PT — Parity Type
PE — Parity Enable
M — Mode Select
WAKE — Wakeup by Address Mark
TIE — Transmit Interrupt Enable
TCIE — Transmit Complete Interrupt Enable
RIE — Receiver Interrupt Enable
ILIE — Idle-Line Interrupt Enable
TE — Transmitter Enable
RE — Receiver Enable
MC68331TS/D
When parity is enabled, PT determines whether parity is even or odd for both the receiver and the trans-
mitter.
PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re-
ceived parity bit is not correct, the SCI sets the PF error flag in SCSR.
When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which re-
sults in either seven or eight bits of user data, depending on the condition of M bit. The following table
lists the available choices.
The transmitter retains control of the TXD pin until completion of any character transfer in progress
when TE is cleared.
0 = Even parity
1 = Odd parity
0 = SCI parity disabled
1 = SCI parity enabled
0 = SCI frame: 1 start bit, 8 data bits, 1 stop bit (10 bits total)
1 = SCI frame: 1 start bit, 9 data bits, 1 stop bit (11 bits total)
0 = SCI receiver awakened by idle-line detection
1 = SCI receiver awakened by address mark (last bit set)
0 = SCI TDRE interrupts inhibited
1 = SCI TDRE interrupts enabled
0 = SCI TC interrupts inhibited
1 = SCI TC interrupts enabled
0 = SCI RDRF interrupt inhibited
1 = SCI RDRF interrupt enabled
0 = SCI IDLE interrupts inhibited
1 = SCI IDLE interrupts enabled
0 = SCI transmitter disabled (TXD pin may be used as I/O)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter)
0 = SCI receiver disabled (status bits inhibited)
1 = SCI receiver enabled
Freescale Semiconductor, Inc.
For More Information On This Product,
M
0
0
1
1
Go to: www.freescale.com
PE
0
1
0
1
8 Data Bits
7 Data Bits, 1 Parity Bit
9 Data Bits
8 Data Bits, 1 Parity Bit
Result
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