MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 18

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

SYPCR —System Protection Control Register
SLVEN —Factory Test Mode Enabled
SHEN[1:0] —Show Cycle Enable
SUPV —Supervisor/Unrestricted Data Space
MM —Module Mapping
IARB[3:0] —Interrupt Arbitration Field
3.2.2 System Protection Control Register
SWE —Software Watchdog Enable
18
RESET:
15
This bit is a read-only status bit that reflects the state of DATA11 during reset.
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
The SUPV bit places the SIM global registers in either supervisor or user data space.
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU pro-
cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,
the SIM IARB field value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is
%0000, which prevents SIM interrupts from being discarded during initialization.
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. This register can be written only once following power-on or reset,
but can be read at any time.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
0 = Registers with access controlled by the SUPV bit are accessible from either the user or super-
1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.
0 = Internal modules are addressed from $7FF000 –$7FFFFF.
1 = Internal modules are addressed from $FFF000 –$FFFFFF.
0 = Software watchdog disabled
1 = Software watchdog enabled
visor privilege level.
NOT USED
SHEN
00
01
10
11
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Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
8
SWE
7
1
MODCLK
SWP
Action
6
5
0
SWT
4
0
HME
3
0
BME
2
0
MC68331TS/D
$YFFA21
1
0
BMT
0
0