MCF5280CVM66J Freescale Semiconductor, MCF5280CVM66J Datasheet - Page 140
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MCF5280CVM66J
Manufacturer Part Number
MCF5280CVM66J
Description
IC MPU RISC 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5280CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5280CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Power Management
7.2.3.2
The LPCR controls chip operation and module operation during low-power modes.
7-4
Bits
7–6
4–3
5
2
1
0
Low-Power Control Register (LPCR)
Address
Reset
Field
R/W
STPMD
LVDSE
Name
LPMD
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
—
—
—
Figure 7-2. Low-Power Control Register (LPCR)
7
LPMD
Low-power mode select. Used to select the low-power mode the chip
enters once the ColdFire CPU executes the STOP instruction. These bits
must be written prior to instruction execution for them to take effect. The
LPMD[1:0] bits are readable and writable in all modes.
the four different power modes that can be configured with the LPMD bit
field.
Reserved, should be cleared.
PLL/CLKOUT stop mode. Controls PLL and CLKOUT operation in stop
mode as shown in
Reserved, should be cleared.
LDV standby enable. Controls whether the PMM enters VREG Standby
Mode (LVD disabled) or VREG Pseudo-Standby (LVD enabled) mode when
the PMM receives a power down request. This bit has no effect if the
RCR[LVDE] bit is a logic 0.
1 VREG Pseudo-Standby mode (LVD enabled on power down request).
0 VREG Standby mode (LVD disabled on power down request).
Reserved, should be cleared.
Table 7-4. LPCR Field Descriptions
Table 7-5. Low-Power Modes
6
LPMD[1:0]
11
10
01
00
—
5
IPSBAR + 0x0011_0007
Table 7-6
0000_0010
4
STPMD
R/W
Description
3
DOZE
Mode
STOP
WAIT
RUN
—
2
LVDSE
1
Table 7-5
—
Freescale Semiconductor
0
illustrates
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