MCF5280CVM66J Freescale Semiconductor, MCF5280CVM66J Datasheet - Page 53

• Manufacturer Part Number: MCF5280CVM66J
• Description: IC MPU RISC 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

2.2.5
The PC contains the currently executing instruction address. During instruction execution and exception
processing, the processor automatically increments contents of the PC or places a new value in the PC, as
appropriate. The PC is a base address for PC-relative operand addressing.
The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.
2.2.6
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. The CACR is described in
2.2.7
The access control registers define attributes for user-defined memory regions. These attributes include the
definition of cache mode, write protect, and buffer write enables. The ACRs are described in
“Access Control Registers (ACR0, ACR1).”
2.2.8
The VBR contains the base address of the exception vector table in memory. To access the vector table,
the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are
not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on
a 1 MB boundary.
Freescale Semiconductor
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDM: 0x80F (PC)
BDM: 0x801 (VBR)
W
W
R
R
Program Counter (PC)
Cache Control Register (CACR)
Access Control Registers (ACRn)
Vector Base Register (VBR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Base Address
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 2-6. Program Counter Register (PC)
Figure 2-7. Vector Base Register (VBR)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Section 4.2.1, “Cache Control Register (CACR).”
Address
Access: Supervisor read/write
8
8
7
7
Access: User read/write
6
6
5
5
BDM read/write
BDM read/write
4
4
3
3
Section 4.2.2,
2
2
ColdFire Core
1
1
0
0
2-7