MCF5280CVM66J Freescale Semiconductor, MCF5280CVM66J Datasheet - Page 225
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MCF5280CVM66J
Manufacturer Part Number
MCF5280CVM66J
Description
IC MPU RISC 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5280CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5280CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 13
External Interface Module (EIM)
This chapter describes data-transfer operations, error conditions, and reset operations.
“Synchronous DRAM Controller
13.1
The following list summarizes bus operation features:
13.2
Table 13-1
Freescale Semiconductor
•
•
•
•
•
Up to 24 bits of address and 32 bits of data
Access 8-, 16-, and 32-bit data port sizes
Generates byte, word, longword, and line-size transfers
Burst and burst-inhibited transfer support
Optional internal termination for external bus cycles
Features
Bus and Control Signals
summarizes the bus signals described in
1
These signals change after the falling edge. In the Electrical Specifications, these signals are
specified off of the rising edge because CLKIN is squared up internally.
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used
for the bus.
Signal Name
CS[6:0]
SIZ[1:0]
A[23:0]
D[31:0]
OE
BS
R/W
TIP
TS
TA
1
1
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Address bus
Byte selects
Chip selects
Data bus
Output enable
Read/write
Transfer size
Transfer acknowledge
Transfer in progress
Transfer start
Table 13-1. ColdFire Bus Signal Summary
Module,” describes DRAM cycles.
Description
NOTE
Chapter 14, “Signal
I/O
I/O
O
O
O
O
O
O
O
O
I
Descriptions”.
Rising
Falling
Falling
Rising
Falling
Rising
Rising
Rising
Rising
Rising
CLKOUT Edge
Chapter 15,
13-1
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