M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 28

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3851 Group
The serial I/O2 can be operated only as the clock synchronous type.
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits se-
lecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding S
format or N-channel open-drain output format can be selected by the
P0
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 0017
tion of data transfer, the level of the S
ance automatically but bit 7 of the serial I/O2 control register 2 is not
set to “1” automatically.
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the S
not go to high impedance after completion of data transfer.
To cause the S
the external clock is selected, set bit 7 of the serial I/O2 control reg-
ister 2 to “1” when S
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to “0” and the S
the active state.
Regardless of the internal clock to external clock, the interrupt re-
quest bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control regis-
ter 1 is LSB first, or a fractional number of bits close to LSB if the
transfer direction selection bit is MSB first. For the remaining bits, the
previously received data is shifted.
At transmit operation using the clock synchronous serial I/O, the S
signal can be output by comparing the state of the transmit pin S
with the state of the receive pin S
the transfer clock. If the output level of the S
input level to the S
is output. At this time, an INT
ated. Select a valid edge by bit 2 of the interrupt edge selection reg-
ister (address 003A
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 0015
The serial I/O2 control registers 1 and 2 are containing various se-
lection bits for serial I/O2 control as shown in Figure 23.
Rev.1.01
SERIAL I/O2
1
/S
OUT2
, P0
OUT2
Oct 15, 2003
OUT2
(Built-in 24 KB or more ROM)
2
/S
and S
IN2
16
CLK2
CLK2
pin to go to high impedance in the case where
pin, “L” is output from the S
).
CLK2
is “H” after completion of data transfer. After
16,
P-channel output disable bit (b7) of
being output pins, either CMOS output
2
0016
page 26 of 89
interrupt request can also be gener-
IN2
in synchronization with a rise of
16
OUT2
pin goes to high imped-
OUT2
CMP2
OUT2
pin is equal to the
16
). After comple-
pin. If not, “H”
OUT2
pin is put into
pin does
CMP2
OUT2
Fig. 23 Structure of Serial I/O2 control registers 1, 2
b7
b7
b 0
b0
S e r i a l I / O 2 c o n t r o l r e g i s t e r 1
( S I O 2 C O N 1 : a d d r e s s 0 0 1 5
S e r i a l I / O 2 c o n t r o l r e g i s t e r 2
( S I O 2 C O N 2 : a d d r e s s 0 0 1 6
I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s
b 2 b 1 b 0
0 0 0 : f ( X
0 0 1 : f ( X
0 1 0 : f ( X
0 1 1 : f ( X
1 1 0 : f ( X
1 1 1 : f ( X
S e r i a l I / O 2 p o r t s e l e c t i o n b i t
0 : I / O p o r t
1 : S
S
0 : P 0
1 : P 0
T r a n s f e r d i r e c t i o n s e l e c t i o n b i t
0 : L S B f i r s t
1 : M S B f i r s t
S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t
0 : E x t e r n a l c l o c k
1 : I n t e r n a l c l o c k
P 0
0 : C M O S o u t p u t ( i n o u t p u t m o d e )
1 : N - c h a n n e l o p e n - d r a i n o u t p u t ( i n o u t p u t m o d e )
Optional transfer bits
b2 b1 b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
0: P4
1: S
S
0: Output active
1: Output high-impedance
R D Y 2
OUT2
1
/ S
O U T 2
CMP2
3
3
O U T 2 ,
3
o u t p u t e n a b l e b i t
p i n i s n o r m al I / O p i n
p i n i s S
pin control bit (P0
I/O
, S
output
C L K 2
P 0
I N
I N
I N
I N
I N
I N
) / 8 ( f ( X
) / 1 6 ( f ( X
) / 3 2 ( f ( X
) / 6 4 ( f ( X
) / 1 2 8 f ( X
) / 2 5 6 ( f ( X
2
R D Y 2
/ S
o u t p u t p i n
C L K 2
o u t p u t p i n
C I N
C I N
C I N
C I N
P - c h a n n e l o u t p u t d i s a b l e b i t
C I N
C I N
) / 8 i n l o w - s p e e d m o d e )
) / 1 6 i n l o w - s p e e d m o d e )
) / 3 2 i n l o w - s p e e d m o d e )
) / 6 4 i n l o w - s p e e d m o d e )
) / 1 2 8 i n l o w - s p e e d m o d e )
1
1 6
) / 2 5 6 i n l o w - s p e e d m o d e )
)
1 6
)
)