M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 32

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
Set a slave address in the high-order 7 bits of the I
register (address 002C
Set the ACK return mode and SCL = 100 kHz by setting “85
in the I
transmission/reception mode can become initializing condition.
Set a communication enable status by setting “08
control register (address 002E
Confirm the bus free condition by the BB flag of the I
register (address 002D
high-order 7 bits of the I
and set “0” in the least significant bit.
Set “F0
ate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
Set transmit data in the I
At this time, an SCL and an ACK clock automatically occur.
When transmitting control data of more than 1 byte, repeat step
Set “D0
ate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Set a slave address in the high-order 7 bits of the I
Set a communication enable status by setting “08
When a START condition is received, an address comparison is
•When all transmitted addresses are “0” (general call):
• When the transmitted addresses agree with the address set
• In the cases other than the above AD0 and AAS of the I
Set dummy data in the I
When receiving control data of more than 1 byte, repeat step
When a STOP condition is detected, the communication ends.
Set “00
Set the address data of the destination of transmission in the
Set the no ACK clock mode and SCL = 400 kHz by setting
Set “00
register (address 002C
“65
transmission/reception mode can become initializing condition.
control register (address 002E
performed.
AD0 of the I
and an interrupt request signal occurs.
in
ASS of the I
and an interrupt request signal occurs.
tus register (address 002D
request signal occurs.
.
16
:
” in the I
2
16
16
16
16
C clock control register (address 002F
” in the I
” in the I
” in the I
” in the I
2
2
2
C status register (address 002D
C status register (address 002D
C clock control register (address 002F
2
2
2
2
C status register (address 002D
C status register (address 002D
C status register (address 002D
C status register (address 002D
16
16
16
2
2
2
C data shift register (address 002B
) and “0” into the RWB bit.
).
C data shift register (address 002B
C data shift register (address 002B
) and “0” in the RWB bit.
16
16
16
) are set to “0” and no interrupt
).
).
16
16
16
).
) is set to “1”
) is set to “1”
16
16
16
16
2
2
” in the I
” in the I
16
16
C address
) to gener-
) to gener-
C address
16
2
) so that
) so that
C status
).
2
C sta-
16
16
16
16
2
2
C
C
).
).
”
)
.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(Built-in 16 KB ROM)
3851 Group
29