M30620FCPFP#U9C Renesas Electronics America, M30620FCPFP#U9C Datasheet - Page 301
![IC M16C/62P MCU FLSH 128K 100QFP](/photos/12/41/124183/m30620fcpfp_u9c_sml.jpg)
M30620FCPFP#U9C
Manufacturer Part Number
M30620FCPFP#U9C
Description
IC M16C/62P MCU FLSH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCPFP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCPFP#U9CM30620FCPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
22.3.4
22.3.4.1
22.3.4.2
22.3.4.3
22.3.4.4
22.3.4.5
22.3.4.6
22.3.4.7
22.3.4.8
Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to a CPU clock frequency
of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1
register to “1” (wait state).
The following instructions cannot be used in EW0 mode because the CPU tries to read data in the flash
memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
To set the FMR01, FMR02 or FMR11 bit to “1”, write “1” after first setting the bit to “0”. Do not generate an
interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction to set the bit to “1”.
Set the bit while an “H” signal is applied to the NMI pin.
If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash
memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error occurs,
rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode.
Avoid rewriting any block in which the rewrite control program is stored.
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0” (auto
programming or auto erasing).
•
•
•
•
•
•
Jan 10, 2006
To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM
area.
The NMI and watchdog timer interrupts are available since the FMR0 and FMR1 registers are forcibly reset
when either interrupt occurs. Allocate the jump addresses for each interrupt service routines to the fixed
vector table. Flash memory rewrite operation is suspended when the NMI or watchdog timer interrupt
occurs. Execute the rewrite program again after exiting the interrupt routine.
The address match interrupt is not available since the CPU tries to read data in the flash memory.
Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt
during the auto program or auto erase period.
Do not use the watchdog timer interrupt.
The NMI interrupt is available since the FMR0 and FMR1 registers are forcibly reset when the interrupt
occurs. Allocate the jump address for the interrupt service routine to the fixed vector table. Flash memory
rewrite operation is suspended when the NMI interrupt occurs. Execute the rewrite program again after
exiting the interrupt service routine.
Precautions on CPU Rewrite Mode
Operating Speed
Prohibited Instructions
Interrupts (EW0 mode)
Interrupts (EW1 mode)
22.3.4.5 How to Access
22.3.4.6 Rewriting in the User ROM Area (EW0 mode)
22.3.4.7 Rewriting in the User ROM Area (EW1 mode)
22.3.4.8 DMA Transfer
Page 284 of 390
22. Flash Memory Version
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