M30620FCPFP#U9C Renesas Electronics America, M30620FCPFP#U9C Datasheet - Page 86
![IC M16C/62P MCU FLSH 128K 100QFP](/photos/12/41/124183/m30620fcpfp_u9c_sml.jpg)
M30620FCPFP#U9C
Manufacturer Part Number
M30620FCPFP#U9C
Description
IC M16C/62P MCU FLSH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCPFP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCPFP#U9CM30620FCPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 8.8
NOTES:
SFR
Internal
RAM,
ROM
External
Area
Area
1. To use the RDY signal, set this bit to “0”.
2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait
3. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by
4. After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0”
5. When PM17 bit is set to “1” and accesses an external area, set the CSiW (i=0 to 3) bits to “0” (with
state).
the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the
PM20 bit to “0” (2 wait cycles).
(with wait state), and the CSE register is set to “00h” (one wait state for CS0 to CS3). Therefore, the
internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
wait state).
Jan 10, 2006
Separate
Bus
Multiplexed
Bus
Bus Mode
(2)
−
−
−
−
Bit and Bus Cycle Related to Software Wait
PM20 Bit
Register
PM2
1
0
−
−
−
−
−
−
−
−
−
−
−
Page 69 of 390
PM17 Bit
Register
PM1
−
−
0
1
0
−
−
−
1
−
−
−
1
(5)
CSR Register
CS3W Bit
CS2W Bit
CS1W Bit
CS0W Bit
1
0
0
0
0
0
0
0
0
−
−
−
−
(1)
(1)
(1)
(1)
CSE31W to CSE30W Bit
CSE21W to CSE20W Bit
CSE11W to CSE10W Bit
CSE01W to CSE00W Bit
CSE Register
00b
00b
01b
10b
00b
00b
01b
10b
00b
−
−
−
−
Software
No wait
No wait
2 waits
3 waits
2 waits
3 waits
1 wait
1 wait
1 wait
1 wait
1 wait
Wait
−
−
2 BCLK cycles
3 BCLK cycles
1 BCLK cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
(write)
2 BCLK cycle
3 BCLK cycles
4 BCLK cycle
2 BCLK cycle
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
(read)
Bus Cycle
(4)
(4)
(3)
(3)
8. Bus
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