HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 262

• Manufacturer Part Number: HD6473228F10V
• Description: MCU 5V 32K,PB-FREE 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473228F10V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates
the number of cycles of each type occurring in each instruction. The total number of states required
for execution of an instruction can be calculated from these two tables as follows:
Execution states = I S
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
2. JSR @@30
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Execution status
(instruction cycle)
Instruction fetch
Branch address read S
Stack operation
Byte data access
Word data access
Internal operation
Notes: 1. m: Number of wait states inserted in access to external device.
From table A-4: I = L = 2,
From table A-3: S
Number of states required for execution: 2 8 + 2 3 =22
From table A-4: I = 2,
From table A-3: S
Number of states required for execution: 2 8 + 1 8 + 1 8 = 32
2. The byte data access cycle to an external device by the MOVFPE and MOVTPE
instructions requires 9 to 16 states since it is synchronized with the E clock. See
section 13, E-Clock Interface for timing details.
S
S
S
S
S
I
I
I
J
K
L
M
N
I
= 8,
= S
+ J S
J
= S
J = K = 1,
S
J
K
2
On-chip memory
L
+ K S
J = K = M = N= 0
= 3
= 8
K
L = M = N = 0
+ L S
266
L
Access location
+ M S
On-chip reg. field
6
3
6
2
M
+ N S
N
External memory
6 + 2m
3 + m (note 2)
6 + 2m