HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 820

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Register
TSR0—Timer Status Register 0
Rev. 7.00 Sep 21, 2005 page 794 of 878
REJ09B0259-0700
Bit
Initial value
Read/Write
Note: Only 0 can be written, to clear the flag.
*
Overflow flag
0 [Clearing condition]
1 [Setting condition]
Read OVF when OVF = 1, then write 0 in OVF
TCNT overflowed from H'FFFF to H'0000 or
underflowed from H'0000 to H'FFFF
—
—
7
1
Input capture/compare match flag B
0 [Clearing condition]
1 [Setting conditions]
Read IMFB when IMFB = 1, then write 0 in IMFB
TCNT = GRB when GRB functions as an output compare
register.
TCNT value is transferred to GRB by an input capture
signal, when GRB functions as an input capture register.
Input capture/compare match flag A
—
—
6
1
0 [Clearing condition]
1 [Setting conditions]
Read IMFA when IMFA = 1, then write 0 in IMFA
TCNT = GRA when GRA functions as an output compare
register.
TCNT value is transferred to GRA by an input capture
signal, when GRA functions as an input capture register.
—
—
5
1
—
—
4
1
—
—
3
1
H'67
R/(W)
OVF
2
0
*
R/(W)
IMFB
1
0
*
R/(W)
IMFA
0
0
ITU0
*