D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 142
D64F3437TFLH16V
Manufacturer Part Number
D64F3437TFLH16V
Description
MCU 5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of D64F3437TFLH16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D64F3437TFLH16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 142 of 755
- Download datasheet (4Mb)
7.3
7.3.1
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7.5. The pin
functions differ depending on the operating mode.
Port 2 has built-in, programmable MOS input pull-up transistors that can be used in modes 2 and
3.
Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and
darlington transistors.
110
Port 2
Overview
Port 2
Port 2 pins
P2
P2
P2
P2
P2
P2
P2
P2
Figure 7.5 Port 2 Pin Configuration
7
6
5
4
3
2
1
0
/A
/A
/A
/A
/A
/A
/A
/A
15
14
13
12
11
10
9
8
Pin configuration
in mode 1
(expanded mode
with on-chip ROM
disabled)
A
A
A
A
A
A
A
A
Pin configuration in mode 3
(single-chip mode)
P2
P2
P2
P2
P2
P2
P2
P2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
Pin configuration
in mode 2
(expanded mode
with on-chip ROM
enabled)
A
A
A
A
A
A
A
A
15
14
13
12
11
10
9
8
(output)/P2
(output)/P2
(output)/P2
(output)/P2
(output)/P2
(output)/P2
(output)/P2
(output)/P2
7
6
5
4
3
2
1
0
(input)
(input)
(input)
(input)
(input)
(input)
(input)
(input)
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