D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 357
D64F3437TFLH16V
Manufacturer Part Number
D64F3437TFLH16V
Description
MCU 5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of D64F3437TFLH16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D64F3437TFLH16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.2.7
Bit
Initial value
Slave Read/Write
Host Read/Write
ODR2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the
host processor. The ODR2 contents are output on the host data bus when HA
and IOR is low.
The initial values of ODR2 after a reset or standby are undetermined.
14.2.8
Bit
Initial value
Slave Read/Write
Host Read/Write
STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3,
1, and 0 are read-only bits to both the host and slave processors.
STR2 is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D): Receives the HA
and indicates whether IDR2 contains data or a command.
Bit 3: C/D
0
1
Output Data Register 2 (ODR2)
Status Register 2 (STR2)
ODR7
Description
Contents of IDR2 are data
Contents of IDR2 are a command
DBU
R/W
R/W
—
R
R
7
7
0
ODR6
DBU
R/W
R/W
—
R
R
6
6
0
ODR5
DBU
R/W
R/W
—
R
R
5
5
0
0
ODR4
input when the host processor writes to IDR2,
DBU
R/W
R/W
—
R
R
4
4
0
ODR3
R/W
C/D
—
R
R
R
3
3
0
ODR2
DBU
R/W
R/W
—
R
R
2
2
0
0
is low, CS
ODR1
R/W
IBF
—
R
R
R
1
1
0
(Initial value)
2
is low,
ODR0
OBF
R/W
—
R
R
R
0
0
0
325
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