D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 200
D64F3437TFLH16V
Manufacturer Part Number
D64F3437TFLH16V
Description
MCU 5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of D64F3437TFLH16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
D64F3437TFLH16V
Manufacturer:
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Quantity:
10 000
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Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2: BUFEB
0
1
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for FRC. External clock pulses are counted on the rising edge of
signals input to pin FTCI.
Bit 1: CKS1
0
1
8.2.7
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, and switches access between output compare registers A and B.
TOCR is initialized to H'E0 by a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4: OCRS
0
1
168
Bit
Initial value
Read/Write
Timer Output Compare Control Register (TOCR)
Description
ICRD is used for input capture D.
ICRD is used as a buffer register for input capture B.
Bit 0: CKS0
0
1
0
1
Description
OCRA is selected.
OCRB is selected.
—
—
7
1
—
—
6
1
Description
ø
ø
ø
External clock source (rising edge)
—
—
P
P
P
5
1
/2 internal clock source
/8 internal clock source
/32 internal clock source
OCRS
R/W
4
0
OEA
R/W
3
0
OEB
R/W
2
0
OLVLA
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
OLVLB
R/W
0
0
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