DF2166VT33 Renesas Electronics America, DF2166VT33 Datasheet - Page 664
DF2166VT33
Manufacturer Part Number
DF2166VT33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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• Flash Code Control Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence
during programming or erasing flash memory and the download of on-chip program.
Bit
7
6, 5
4
Rev. 3.00, 03/04, page 622 of 830
Bit Name
FWE
FLER
Initial
Value
1/0
All 0
0
R/W
R
R/W
R
Description
Flash Program Enable
Monitors the signal level input to the FWE pin and
enables or disables programming/erasing flash memory.
0: Programming/erasing disabled
1: Programming/erasing enabled
Reserved
The initial value should not be changed.
Flash Memory Error
Indicates an error occurs during programming and
erasing flash memory. When FLER is set to 1, flash
memory enters the error protection state.
When FLER is set to 1, high voltage is applied to the
internal flash memory. To reduce the damage to flash
memory, the reset must be released after the reset
period of 100 µs which is longer than normal.
0: Flash memory operates normally.
[Clearing condition]
•
1: An error occurs during programming/erasing flash
[Setting conditions]
•
•
•
•
Programming/erasing protection for flash memory
(error protection) is invalid.
memory.
Programming/erasing protection for flash memory
(error protection) is valid.
At a reset or in hardware standby mode
When an interrupt, such as NMI, occurs during
programming/erasing flash memory.
When the flash memory is read during
programming/erasing flash memory (including a
vector read or an instruction fetch).
When the SLEEP instruction is executed during
programming/erasing flash memory (including
software-standby mode)
When a bus master other than the CPU, such as the
DTC, gets bus mastership during
programming/erasing flash memory.
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