HD6417760BP200DQ Renesas Electronics America, HD6417760BP200DQ Datasheet - Page 367

IC SUPERH MPU ROMLESS 256BGA

HD6417760BP200DQ

Manufacturer Part Number
HD6417760BP200DQ
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BP200DQ

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BP200DQ
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note:
Table 10.9 WCR3 and WCR4 Settings for Area 1
Note: Values other than the combinations listed above are illegal settings.
Bit
31 to 2 ⎯
1
0
WCR3
A1RDH
0
1
* Only use the combinations listed in table 10.9 for the settings.
Bit
Name
CSH1*
CSH0*
A1H1
0
1
0
1
0
1
Initial
Value
All 0
0
0
R/W
R
R/W
R/W
A1H0
0
1
0
1
0
1
0
1
1
0
1
Description
Reserved
These bits are always read as 0, and the write value
should always be 0.
CS Hold Cycle Setting
Specifies the number of wait cycles inserted during data
hold after CS1 is negated.
00:
01:
10:
11:
If a value other than 00 is set, set WCR3.A1RDH to 1.
Wait cycles to be inserted
0
1
2
3
WCR4
CSH1
0
0
0
1
Rev. 2.00 Feb. 12, 2010 Page 283 of 1330
CSH0
0
0
1
0
1
REJ09B0554-0200

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