M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet - Page 13

• Manufacturer Part Number: M37632EFFP#U2
• Description: IC 740 MCU 80QFP
• Manufacturer: Renesas Electronics America

Specifications of M37632EFFP#U2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CENTRAL PROCESSING UNIT
[ X modified operation mode flag T ] ----------------------- Bit 5
[ Overflow flag V ] ------------------------------------------------- Bit 6
[ Negative flag N ] ------------------------------------------------- Bit 7
Table 2.5.1 Instructions to set/clear each flag of processor status register
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Set instruction
Clear instruction
This flag determines whether arithmetic operations are performed via the Accumulator or
directly on a memory location. When the flag is set to “0”, arithmetic operations are
performed between the Accumulator and memory. When “1”, arithmetic operations are
performed directly on a memory location.
This flag is set by the SET instruction and is cleared by the CLT instruction.
This flag is set to “1” when an overflow occurs as a result of a signed arithmetic operation.
An overflow occurs when the result of an addition or subtraction exceeds +127 (7F
–128 (80
The CLV instruction clears the Overflow Flag. There is no set instruction.
The overflow flag is also set during the BIT instruction when bit 6 of the value being tested
is “1.”
This flag is set to match the sign bit (bit 7) of the result of a data or arithmetic operation.
This flag can be used to determine whether the results of arithmetic operations are positive
or negative, and also to perform a simple bit test.
(1) When the T flag = 0
(2) When the T flag = 1
Overflows do not occur when the result of an addition or subtraction is equal to or
smaller than the above numerical values, or for additions involving values with different
signs.
16
A ← ← ← ← ← A * M2
M1 ← ← ← ← ← M1 * M2
) respectively.
* : indicates an arithmetic operation
A: accumulator contents
M2: contents of a memory location specified by the addressing mode of the
* : indicates arithmetic operation
M1: contents of a memory location, designated by the contents of Index
M2: contents of a memory location specified by the addressing mode of
Flag C
SEC
CLC
arithmetic operation
page 5 of 185
Register X.
arithmetic operation.
Flag Z
Flag I
SEI
CLI
Flag D
SED
CLD
Processor Status Register (PS)
Flag B
Flag T
SET
CLT
Flag V
CLV
Flag N
16
) or