M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet - Page 33

• Manufacturer Part Number: M37632EFFP#U2
• Description: IC 740 MCU 80QFP
• Manufacturer: Renesas Electronics America

Specifications of M37632EFFP#U2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INSTRUCTIONS
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Addressing mode :
Instructions :
Function :
Example :
designation
Zero page
When the bit 5 at address 04
is cleared, jumps to address *–12.
Zero Page Bit Relative
page 25 of 185
Zero Page Bit Relative
Specifies the address of a memory location where the
next Op-Code is located.
The bit position is designated by the high-order three
bits of the Op-Code. The address in the Zero Page
memory location is determined by using Operand I as
low-order byte of the address and 00
order byte. If the branch condition is satisfied, Oper-
and Il and the Program Counter are added. The result
of this addition is the address in the memory location.
When the branch condition is not satisfied, the next
instruction is executed.
BBC, BBS
Mnemonic
1
Bit designation
Operand II (F1
Operand I (04
0
executed next
Address to be
bit 5
Zero page
Memory
0
1 1
∆ ∆ ∆ ∆ ∆ BBC∆ ∆ ∆ ∆ ∆ 5,$04,∗ ∗ ∗ ∗ ∗ –12
Op-code(B7
0
1
16
1 1
16
)
16
)
)
00
04
*–12
FF
*+3
*
16
16
16
16
Jump
Decimal
designation
When the bit 5 at address 04
is set, goes to address *+3.
Zero page
Machine language
1
Bit designation
Operand II (F1
Operand I (04
B7
0
Address to be
executed next
bit 5
Zero page
Memory
1
1 1
16
Op-code(B7
Addressing mode
0
04
16
1
16
16
1 1
as the high-
16
)
16
)
F1
)
00
04
FF
*+3
*
16
16
16
16
16