UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 39

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UPD78F9200MA-CAC-A

Manufacturer Part Number
UPD78F9200MA-CAC-A
Description
MCU 8BIT 1KB FLASH 128B RAM
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9200MA-CAC-A

Package / Case
*
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
7
Core Processor
78K0S
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
1KB (1K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F9200MA-CAC-A
Manufacturer:
NEC
Quantity:
20 000
(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
(c) Auxiliary carry flag (AC)
(d) Carry flag (CY)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U18172EJ3V0UD
37

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