MAXQ610A-0000+ Maxim Integrated Products, MAXQ610A-0000+ Datasheet - Page 10

• Manufacturer Part Number: MAXQ610A-0000+
• Description: IC MCU 16BIT 64K IR MOD 32TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ610A-0000+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Infrared, Power-Fail, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFN Exposed Pad
• Processor Series: MAXQ610
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 12 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Controller Family/series: MAXQ
• No. Of I/o's: 24
• Ram Memory Size: 2048Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Embedded Interface Type: JTAG, SPI, USART
• Rohs Compliant: Yes
• Number Of Programmable I/os: 32
• Development Tools By Supplier: MAXQ610-KIT
• Package: 32TQFN EP
• Family Name: MAXQ
• Maximum Speed: 12 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 90-M6800+B01

16-Bit Microcontroller with Infrared Module
A 16-bit-wide internal stack provides storage for program
return addresses and can also be used as general-pur-
pose data storage. The stack is used automatically by
the processor when the CALL, RET, and RETI instruc-
tions are executed and when an interrupt is serviced. An
application can also store values in the stack explicitly by
using the PUSH, POP, and POPI instructions.
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vector-
ing operations increment SP, then store a value at the
location pointed to by SP. The RET, RETI, POP, and
POPI operations retrieve the value at SP and then
decrement SP.
The utility ROM is a 1.024KB block of internal ROM mem-
ory that defaults to a starting address of 8000h. The utility
ROM consists of subroutines that can be called from
application software. These include the following:
• Test routines (internal memory tests, memory loader,
• User-callable routines for fast table lookup
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of system code, or to one of the special rou-
tines mentioned. Routines within the utility ROM are
user accessible and can be called as subroutines by
the application software. More information on the utility
ROM functions is contained in the MAXQ Family User’s
Guide: MAXQ610 Supplement .
An internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
Table 1. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
10
WD[1:0]
etc.)
00
01
10
11
______________________________________________________________________________________
WATCHDOG CLOCK
Sysclk/2
Sysclk/2
Sysclk/2
Sysclk/2
Watchdog Timer
15
18
21
24
Stack Memory
Utility ROM
WATCHDOG INTERRUPT TIMEOUT
174.7ms
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the appli-
cation software. If software is operating correctly, the
counter is periodically reset and never reaches its max-
imum count. However, if software operation is interrupt-
ed, the timer does not reset, triggering a system reset
and optionally a watchdog timer interrupt. This protects
the system against electrical noise or ESD upsets that
could cause uncontrolled processor operation. The
internal watchdog timer is an upgrade to older designs
with external watchdog devices, reducing system cost
and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog-timer timeout and the watchdog-timer reset.
The timeout period can be programmed in a range of
2
ed when the timeout period expires if the interrupt is
enabled. All watchdog-timer resets follow the pro-
grammed interrupt timeouts by 512 system clock
cycles. If the watchdog timer is not restarted for another
full interval in this time period, a system reset occurs
when the reset timeout expires. See Table 1.
The dedicated IR timer/counter module simplifies low-
speed IR communication. The IR timer implements two
pins (IRTX and IRRX) for supporting IR transmit and
receive, respectively. The IRTX pin has no correspond-
ing port pin designation, so the standard PD, PO, and
PI port control status bits are not present. However, the
IRTX pin output can be manipulated high or low using
the PWCN.IRTXOUT and PWCN.IRTXOE bits when the
IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of two separate timing enti-
ties: a carrier generator and a carrier modulator. The
21.9ms
2.7ms
15
1.4s
to 2
24
system clock cycles. An interrupt is generat-
IR Carrier Generation and
WATCHDOG INTERRUPT (μs)
WATCHDOG RESET AFTER
Modulation Timer
42.7
42.7
42.7
42.7