MAXQ610A-0000+ Maxim Integrated Products, MAXQ610A-0000+ Datasheet - Page 18

• Manufacturer Part Number: MAXQ610A-0000+
• Description: IC MCU 16BIT 64K IR MOD 32TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ610A-0000+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Infrared, Power-Fail, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFN Exposed Pad
• Processor Series: MAXQ610
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 12 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Controller Family/series: MAXQ
• No. Of I/o's: 24
• Ram Memory Size: 2048Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Embedded Interface Type: JTAG, SPI, USART
• Rohs Compliant: Yes
• Number Of Programmable I/os: 32
• Development Tools By Supplier: MAXQ610-KIT
• Package: 32TQFN EP
• Family Name: MAXQ
• Maximum Speed: 12 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 90-M6800+B01

16-Bit Microcontroller with Infrared Module
Table 2. Power-Fail Detection States During Normal Operation
18
STATE
G
A
B
C
D
E
H
F
I
______________________________________________________________________________________
POWER-FAIL
(Periodically)
(Periodically)
On
On
On
On
On
On
On
On
Off
REGULATOR
INTERNAL
Off
On
On
On
On
Off
On
Off
Off
OSCILLATOR
CRYSTAL
Off
On
On
On
On
Off
On
Off
Off
RETENTION
SRAM
Yes
Yes
—
—
—
—
—
—
—
V
V
Crystal warmup time, t
CPU held in reset.
V
CPU normal operation.
Power drop too short.
Power-fail not detected.
V
PFI is set when V
this state for at least t
fail interrupt is generated (if enabled).
CPU continues normal operation.
V
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
V
Crystal warmup time, t
CPU resumes normal operation from 8000h.
V
Power-fail detected.
CPU goes into reset.
Power-fail monitor is turned on periodically.
V
Device held in reset.
No operation allowed.
DD
DD
RST
DD
DD
POR
POR
POR
< V
> V
> V
< V
< V
< V
< V
< V
RST
RST.
POR.
POR.
DD
DD
DD
DD
.
< V
< V
< V
< V
PFW
RST.
RST.
RST.
RST
COMMENTS
.
< V
PFW
XTAL_RDY
XTAL_RDY
DD
, at which time a power-
< V
PFW
.
.
and maintains