UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 563

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(3) IIC flag register 0 (IICF0)
Remark
This register sets the operation mode of I
This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT0 clear flag (STCF)
and I
The IICRSV bit can be used to enable/disable the communication reservation function.
The STCEN bit can be used to set the initial value of the IICBSY bit.
The IICRSV and STCEN bits can be written only when the operation of I
control register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation clears this register to 00H.
Condition for clearing (ACKD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (STD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock following
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (SPD0 = 0)
• At the rising edge of the address transfer byte’s first
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
ACKD0
address transfer
clock following setting of this bit and detection of a start
condition
SPD0
STD0
0
1
0
1
0
1
2
C bus status flag (IICBSY) are read-only.
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is released.
Bit 7 of IIC control register 0 (IICC0)
Figure 18-6. Format of IIC Status Register 0 (IICS0) (3/3)
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD0 = 1)
• After the SDA0 line is set to low level at the rising edge of
Condition for setting (STD0 = 1)
• When a start condition is detected
Condition for setting (SPD0 = 1)
• When a stop condition is detected
ninth clock of SCL0 line
CHAPTER 18 SERIAL INTERFACE IIC0
2
C bus.
2
C is disabled (bit 7 (IICE0) of the IIC
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