PIC17C756-33I/L Microchip Technology, PIC17C756-33I/L Datasheet - Page 23
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PIC17C756-33I/L
Manufacturer Part Number
PIC17C756-33I/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-33I/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC17C756-33I/L
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 23 of 321
- Download datasheet (3Mb)
TABLE 5-1:
TABLE 5-2:
TABLE 5-3:
5.1.4
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resona-
tors. The total time-out also varies based on oscillator
configuration. Table 5-1 shows the times that are asso-
ciated with the oscillator configuration. Figure 5-5 and
Figure 5-6 display these time-out sequences.
Note 1: When BOR is enabled, else the BOR status bit is unknown
Power-on Reset
Brown-out Reset
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
1997 Microchip Technology Inc.
POR
0
1
1
1
1
1
0
0
x
Configuration
2: The OST is only active when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the
4: When BOR is enabled, else the BOR status bit is unknown.
Oscillator
EC, RC
XT, LF
TIME-OUT SEQUENCE
then executed.
mid-range devices.
BOR
0
1
1
1
1
0
0
0
x
(1)
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Event
TO
1
1
0
0
1
x
0
x
1
Greater of: 96 ms or 1024T
Greater of: 96 ms or 1024T
(3)
GLINTD is set
GLINTD is clear
PD
1
0
1
0
1
x
x
0
1
Power-up
Power-on Reset
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
MCLR Reset during normal operation
Brown-out Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
CLRWDT instruction executed
Preliminary
OSC
OSC
PCH:PCL
PC + 1
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/V
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the reset conditions for some special
registers, while Table 5-4 shows the initialization condi-
tions for all the registers.
(1)
Wake up from
1024T
SLEEP
Event
—
--11 1100
--11 1101
--11 1111
--11 1011
--11 0111
--11 0011
--11 1011
--10 1011
OSC
CPUSTA
(4)
MCLR Reset
—
—
DS30264A-page 23
OST Active
PP
Yes
Yes
Yes
Yes
Yes
No
No
No
pin must be
(2)
(2)
(2)
(2)
BOR
—
—
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