AT90S4433-8PI Atmel, AT90S4433-8PI Datasheet - Page 31
![IC MCU 4K FLSH 8MHZ A/D IT 28DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
AT90S4433-8PI
Manufacturer Part Number
AT90S4433-8PI
Description
IC MCU 4K FLSH 8MHZ A/D IT 28DIP
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheet
1.AT90S4433-8AC.pdf
(126 pages)
Specifications of AT90S4433-8PI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90S4433-8PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Sleep Modes
1042H–AVR–04/03
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK are set. The level and edges on the external
INT1 pin that activate the interrupt are defined in Table 7.
Table 7. Interrupt 1 Sense Control
The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt
is selected, pulses that last longer than one clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 8.
Table 8. Interrupt 0 Sense Control
The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt
is selected, pulses that last longer than one clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-
tion must be executed. The SM bit in the MCUCR Register selects which sleep mode
(Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt
occurs while the MCU is in a sleep mode, the MCU wakes up, executes the interrupt
routine, and resumes execution from the instruction following SLEEP. The contents of
the Register File and I/O memory are unaltered. If a reset occurs during sleep mode, the
MCU wakes up and executes from the Reset Vector.
Note that if a level-triggered interrupt is used for wake-up from Power-down, the low
level must be held for a time longer than the reset delay Time-out period (t
wise, the device will not wake up.
ISC11
ISC01
0
0
1
1
0
0
1
1
ISC10
ISC00
0
1
0
1
0
1
0
1
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
AT90S/LS4433
TOUT
). Other-
31