AT90S4433-8PI Atmel, AT90S4433-8PI Datasheet - Page 65
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AT90S4433-8PI
Manufacturer Part Number
AT90S4433-8PI
Description
IC MCU 4K FLSH 8MHZ A/D IT 28DIP
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheet
1.AT90S4433-8AC.pdf
(126 pages)
Specifications of AT90S4433-8PI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90S4433-8PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Operation
Prescaling
1042H–AVR–04/03
The ADC can operate in two modes: Single Conversion and Free Run mode. In Single
Conversion mode, each conversion will have to be initiated by the user. In Free Run
mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR
bit in ADCSR selects between the two available modes.
The ADMUX Register selects which one of the six analog input channels is to be used
as input to the ADC.
The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR.
The first conversion that is started after enabling the ADC will be preceded by a dummy
conversion to initialize the ADC. To the user, the only difference will be that this conver-
sion takes 12 clock cycles more than a normal conversion.
A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.
This bit will stay high as long as the conversion is in progress and be set to zero by hard-
ware when the conversion is completed. If a different data channel is selected while a
conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
As the ADC generates a 10-bit result, two Data Registers, ADCH and ADCL, must be
read to get the result when the conversion is complete. Special data protection logic is
used to ensure that the contents of the Data Registers belong to the same result when
they are read. This mechanism works as follows: When reading data, ADCL must be
read first. Once ADCL is read, ADC access to Data Registers is blocked. This means
that if ADCL has been read and a conversion completes before ADCH is read, none of
the registers are updated and the result from the conversion is lost. When ADCH is
read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt, ADIF, which can be triggered when a conversion com-
pletes. When ADC access to the Data Registers is prohibited between reading of ADCH
and ADCL, the interrupt will trigger even if the result gets lost.
Figure 45. ADC Prescaler
The ADC contains a prescaler, which divides the system clock to an acceptable ADC
clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz.
Applying a higher input frequency will result in a poorer accuracy (see “ADC Character-
istics” on page 71).
The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input fre-
quency from any XTAL frequency above 100 kHz. The prescaler starts counting from
the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler
ADEN
ADPS0
ADPS1
ADPS2
CK
Reset
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
AT90S/LS4433
65