ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 133
![IC AVR MCU 32K 8MHZ COM 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AC
Manufacturer Part Number
ATMEGA323-8AC
Description
IC AVR MCU 32K 8MHZ COM 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AC
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The ADC Control and Status
Register – ADCSR
1457G–AVR–09/03
Table 46. Input Channel Selections (Continued)
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is
turned off. Turning the ADC off while a conversion is in progress, will terminate this
conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, a logical “1” must be written to this bit to start each conver-
sion. In Free Running mode, a logical “1” must be written to this bit to start the first
conversion. The first time ADSC has been written after the ADC has been enabled, or if
ADSC is written at the same time as the ADC is enabled, an extended conversion will
precede the initiated conversion. This extended conversion performs initialization of the
ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. When a extended conversion precedes a real conversion,
ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no
effect.
• Bit 5 – ADFR: ADC Free Running Select
When this bit is set (one) the ADC operates in Free Running mode. In this mode, the
ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will
terminate Free Running mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the Data Registers are
updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-
bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond-
ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the
flag. Beware that if doing a Read-Modify-Write on ADCSR, a pending interrupt can be
disabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-
plete Interrupt is activated.
Bit
$06 ($26)
Read/Write
Initial Value
01000..11101
ADEN
R/W
MUX4..0
7
0
11110
11111
ADSC
R/W
6
0
ADFR
R/W
5
0
ADIF
R/W
4
0
ADIE
R/W
3
0
Single-ended Input
ADPS2
R/W
1.22V (V
0V (AGND)
2
0
Reserved
ATmega323(L)
ADPS1
BG
R/W
1
0
)
ADPS0
R/W
0
0
ADCSR
133
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