ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 37

• Manufacturer Part Number: ATMEGA323-8AC
• Description: IC AVR MCU 32K 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238AC

External Interrupts
MCU Control Register –
MCUCR
1457G–AVR–09/03
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1
(Tim er /Counter1 Overf low Interrupt Enabl e), and TO V1 are set (one), the
Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 changes counting direction at $0000.
• Bit 1– OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0
and the data in OCR0 – Output Compare Register 0. OCF0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF0 is
cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE0
(Timer/Counter0 Compare Match Interrupt Enable), and the OCF0 are set (one), the
Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0
(Tim er /Counter0 Overf low Interrupt Enabl e), and TO V0 are set (one), the
Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter0 changes counting direction at $00.
The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The External Interrupts
can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered
interrupt). This is set up as indicated in the specification for the MCU Control Register –
MCUCR and MCU Control and Status Register – MCUCSR. When the External Interrupt
is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger
as long as the pin is held low.
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammers purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
Bit
$37 ($57)
Read/Write
Initial Value
R/W
SE
7
0
SM2
R/W
6
0
SM1
R/W
5
0
SM0
R/W
4
0
ISC11
R/W
3
0
ISC10
R/W
2
0
ATmega323(L)
ISC01
R/W
1
0
ISC00
R/W
0
0
MCUCR
37