ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 197
![IC AVR MCU 32K 8MHZ COM 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AC
Manufacturer Part Number
ATMEGA323-8AC
Description
IC AVR MCU 32K 8MHZ COM 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AC
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Serial Programming
Algorithm
1457G–AVR–09/03
Both the Flash and EEPROM Memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed.
Figure 98. Serial Programming and Verify
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into $FF.
The Program and EEPROM Memory arrays have separate address spaces:
$0000 to $3FFF for Program memory and $0000 to $03FF for EEPROM Memory.
The device can be clocked by any clock option during Low Voltage Serial Programming.
The minimum low and high periods for the serial clock (SCK) input are defined as
follows:
Low: > 2 CPU clock cycles
High: > 2 CPU clock cycles
When writing serial data to the ATmega323, data is clocked on the rising edge of SCK.
When reading data from the ATmega323, data is clocked on the falling edge of SCK.
See Figure 99, Figure 100, and Table 70 for timing details.
To program and verify the ATmega323 in the Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in Table 69):
1. Power-up sequence:
2. Wait for at least 20 ms and enable Serial Programming by sending the Program-
Apply power between V
RESET and SCK are set to “0”. In accordance with the setting of CKSEL Fuses,
apply a crystal/resonator, external clock or RC network, or let the device run on the
internal RC Oscillator. In some systems, the programmer can not guarantee that
SCK is held low during Power-up. In this case, RESET must be given a positive
pulse of at least two XTAL1 cycles duration after SCK has been set to “0”.
ming Enable serial instruction to pin MOSI/PB5.
MOSI
MISO
SCK
CC
and GND while RESET and SCK are set to “0”. The
PB5
PB6
PB7
RESET
GND
ATmega323
VCC
2.7 - 5.5V
ATmega323(L)
197
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